{"id":452491,"date":"2024-10-20T09:24:49","date_gmt":"2024-10-20T09:24:49","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-802-3cx-2023-5\/"},"modified":"2024-10-26T17:31:06","modified_gmt":"2024-10-26T17:31:06","slug":"ieee-802-3cx-2023-5","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-802-3cx-2023-5\/","title":{"rendered":"IEEE 802.3cx-2023"},"content":{"rendered":"

Amendment Standard – Active. This amendment to IEEE Std 802.3-2022 modifies Clause 30, Clause 45, and Clause 90, and adds Annex 90A to enhance support for time synchronization protocols by providing options for sub-nanosecond reporting of the transmit and receive path data delays, selection of the data delay measurement point, and dynamic reporting of path data delay variation.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nFront Cover <\/td>\n<\/tr>\n
2<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
11<\/td>\nIntroduction <\/td>\n<\/tr>\n
14<\/td>\nContents <\/td>\n<\/tr>\n
18<\/td>\n1. Introduction
1.5 Abbreviations <\/td>\n<\/tr>\n
19<\/td>\n30. Management
30.2 Managed objects
30.2.5 Capabilities <\/td>\n<\/tr>\n
20<\/td>\n30.13 Management for oTimeSync entity
30.13.1 TimeSync entity managed object class
30.13.1.1 aTimeSyncCapabilityNsTX
30.13.1.2 aTimeSyncCapabilityNsRX <\/td>\n<\/tr>\n
21<\/td>\n30.13.1.3 aTimeSyncDelayNsTXmax
30.13.1.4 aTimeSyncDelayNsTXmin <\/td>\n<\/tr>\n
22<\/td>\n30.13.1.5 aTimeSyncDelayNsRXmax
30.13.1.6 aTimeSyncDelayNsRXmin <\/td>\n<\/tr>\n
23<\/td>\n30.13.1.7 aTimeSyncCapabilitySubNsTX
30.13.1.8 aTimeSyncCapabilitySubNsRX
30.13.1.9 aTimeSyncDelaySubNsTXmax <\/td>\n<\/tr>\n
24<\/td>\n30.13.1.10 aTimeSyncDelaySubNsTXmin
30.13.1.11 aTimeSyncDelaySubNsRXmax <\/td>\n<\/tr>\n
25<\/td>\n30.13.1.12 aTimeSyncDelaySubNsRXmin
30.13.1.13 aTimeSyncCapabilityDdmp
30.13.1.14 aTimeSyncSelectionDdmp <\/td>\n<\/tr>\n
26<\/td>\n30.13.1.15 aTimeSyncCapabilityMultiplePcsLane
30.13.1.16 aTimeSyncCapabilityDynamicPathDataDelay <\/td>\n<\/tr>\n
27<\/td>\n45. Management Data Input\/Output (MDIO) Interface
45.2 MDIO Interface registers
45.2.1 PMA\/PMD registers
45.2.1.175 TimeSync PMA\/PMD capability (Register 1.1800) <\/td>\n<\/tr>\n
28<\/td>\n45.2.1.176 TimeSync PMA\/PMD transmit path data delay (Registers 1.1801, 1.1802, 1.1803, 1.1804, 1.1809, and 1.1810) <\/td>\n<\/tr>\n
29<\/td>\n45.2.1.177 TimeSync PMA\/PMD receive path data delay (Registers 1.1805, 1.1806, 1.1807, 1.1808, 1.1811, and 1.1812) <\/td>\n<\/tr>\n
30<\/td>\n45.2.2 WIS registers <\/td>\n<\/tr>\n
31<\/td>\n45.2.2.20 TimeSync WIS capability (Register 2.1800)
45.2.2.21 TimeSync WIS transmit path data delay (Registers 2.1801, 2.1802, 2.1803, 2.1804, 2.1809, and 2.1810) <\/td>\n<\/tr>\n
32<\/td>\n45.2.2.22 TimeSync WIS receive path data delay (Registers 2.1805, 2.1806, 2.1807, 2.1808, 2.1811, and 2.1812) <\/td>\n<\/tr>\n
34<\/td>\n45.2.3 PCS registers
45.2.3.67 TimeSync PCS capability (Register 3.1800) <\/td>\n<\/tr>\n
35<\/td>\n45.2.3.67.1 Data delay measurement point ability (3.1800.13:12)
45.2.3.67.2 Multilane ability (3.1800.11) <\/td>\n<\/tr>\n
36<\/td>\n45.2.3.67.3 PCS dynamic path data delay ability (3.1800.10)
45.2.3.67.4 TimeSync transmit path data delay ability, in sub-ns (3.1800.3)
45.2.3.67.5 TimeSync receive path data delay ability, in sub-ns (3.1800.2)
45.2.3.67.6 TimeSync transmit path data delay ability, in ns (3.1800.1)
45.2.3.67.7 TimeSync receive path data delay ability, in ns (3.1800.0)
45.2.3.68 TimeSync PCS transmit path data delay (Registers 3.1801, 3.1802, 3.1803, 3.1804, 3.1809, and 3.1810) <\/td>\n<\/tr>\n
37<\/td>\n45.2.3.69 TimeSync PCS receive path data delay (Registers 3.1805, 3.1806, 3.1807, 3.1808, 3.1811, and 3.1812) <\/td>\n<\/tr>\n
38<\/td>\n45.2.3.69a TimeSync PCS configuration (Register 3.1813) <\/td>\n<\/tr>\n
39<\/td>\n45.2.3.69a.1 Data delay measurement point (3.1813.13)
45.2.4 PHY XS registers
45.2.4.28 TimeSync PHY XS capability (Register 4.1800) <\/td>\n<\/tr>\n
40<\/td>\n45.2.4.29 TimeSync PHY XS transmit path data delay (Registers 4.1801, 4.1802, 4.1803, 4.1804, 4.1809, and 4.1810) <\/td>\n<\/tr>\n
41<\/td>\n45.2.4.30 TimeSync PHY XS receive path data delay (Registers 4.1805, 4.1806, 4.1807, 4.1808, 4.1811, and 4.1812) <\/td>\n<\/tr>\n
42<\/td>\n45.2.5 DTE XS registers <\/td>\n<\/tr>\n
43<\/td>\n45.2.5.28 TimeSync DTE XS capability (Register 5.1800)
45.2.5.28.1 Data delay measurement point ability (5.1800.13:12) <\/td>\n<\/tr>\n
44<\/td>\n45.2.5.28.2 TimeSync transmit path data delay ability, in sub-ns (5.1800.3)
45.2.5.28.3 TimeSync receive path data delay ability, in sub-ns (5.1800.2)
45.2.5.28.4 TimeSync transmit path data delay ability, in ns (5.1800.1)
45.2.5.28.5 TimeSync receive path data delay ability, in ns (5.1800.0)
45.2.5.29 TimeSync DTE XS transmit path data delay (Registers 5.1801, 5.1802, 5.1803, 5.1804, 5.1809, and 5.1810) <\/td>\n<\/tr>\n
45<\/td>\n45.2.5.30 TimeSync DTE XS receive path data delay (Registers 5.1805, 5.1806, 5.1807, 5.1808, 5.1811, and 5.1812) <\/td>\n<\/tr>\n
46<\/td>\n45.2.5.31 TimeSync DTE XS configuration (Register 5.1813) <\/td>\n<\/tr>\n
47<\/td>\n45.2.5.31.1 Data delay measurement point (5.1813.13)
45.2.6 TC registers
45.2.6.14 TimeSync TC capability (Register 6.1800) <\/td>\n<\/tr>\n
48<\/td>\n45.2.6.15 TimeSync TC transmit path data delay (Registers 6.1801, 6.1802, 6.1803, 6.1804, 6.1809, and 6.1810) <\/td>\n<\/tr>\n
49<\/td>\n45.2.6.16 TimeSync TC receive path data delay (Registers 6.1805, 6.1806, 6.1807, 6.1808, 6.1811, and 6.1812) <\/td>\n<\/tr>\n
51<\/td>\n90. Ethernet support for time synchronization protocols
90.2 Overview
90.3 Relationship with other IEEE standards <\/td>\n<\/tr>\n
52<\/td>\n90.4 Time Synchronization Service Interface (TSSI)
90.4.1 Introduction
90.4.1.1 Interlayer service interfaces <\/td>\n<\/tr>\n
53<\/td>\n90.4.1.2 Responsibilities of TimeSync Client
90.4.2 TSSI
90.4.3 Detailed service specification
90.4.3.1 TS_TX.indication primitive <\/td>\n<\/tr>\n
54<\/td>\n90.4.3.1.1 Semantics
90.4.3.1.2 Condition for generation <\/td>\n<\/tr>\n
55<\/td>\n90.4.3.1.3 Effect of receipt
90.4.3.2 TS_RX.indication primitive
90.4.3.2.1 Semantics <\/td>\n<\/tr>\n
56<\/td>\n90.4.3.2.2 Condition for generation
90.4.3.2.3 Effect of receipt
90.5 generic Reconciliation Sublayer (gRS) <\/td>\n<\/tr>\n
57<\/td>\n90.5.1 TS_SFD_Detect_TX TS_DDMP_Detect_TX function <\/td>\n<\/tr>\n
58<\/td>\n90.5.2 TS_SFD_Detect_RX TS_DDMP_Detect_RX function
90.5.3 Dynamic transmit path data delay <\/td>\n<\/tr>\n
59<\/td>\n90.5.4 Dynamic receive path data delay <\/td>\n<\/tr>\n
60<\/td>\n90.6 Overview of management features <\/td>\n<\/tr>\n
62<\/td>\n90.7 Path dData delay measurement <\/td>\n<\/tr>\n
64<\/td>\n90.7.1 FEC and PCS lane distribution functions <\/td>\n<\/tr>\n
65<\/td>\n90.7.2 Alignment marker, codeword marker, and idle insertion\/removal functions
90.7.3 Lane skew <\/td>\n<\/tr>\n
66<\/td>\n90.8 Protocol implementation conformance statement (PICS) proforma for Clause 90, Ethernet support for time synchronization protocols
90.8.3 TSSI indication <\/td>\n<\/tr>\n
68<\/td>\n90.8.4 DDMP selectionData delay reporting <\/td>\n<\/tr>\n
69<\/td>\nAnnex A (informative) Bibliography <\/td>\n<\/tr>\n
70<\/td>\nAnnex 90A (informative) Timestamping accuracy considerations
90A.1 Sub-nanosecond timestamping introduction
90A.2 Sub-nanosecond timestamping background
90A.3 Considerations for use of different data delay measurement points <\/td>\n<\/tr>\n
72<\/td>\n90A.4 Considerations for multiple PCS lane functions
90A.5 Considerations for alignment marker\/codeword marker and idle functions
90A.5.1 Example use of TX_NUM_BIT_CHANGE and PDPDD <\/td>\n<\/tr>\n
73<\/td>\n90A.5.2 Example use of RX_NUM_BIT_CHANGE and PDPDD
90A.5.3 Considerations for implementations without TX_NUM_BIT_CHANGE and RX_NUM_BIT_CHANGE <\/td>\n<\/tr>\n
74<\/td>\n90A.6 Considerations for transmit skew <\/td>\n<\/tr>\n
75<\/td>\n90A.7 General method for dealing with repeating delay variation patterns <\/td>\n<\/tr>\n
79<\/td>\nBack Cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Ethernet Amendment 6: Media Access Control (MAC) Service Interface and Management Parameters to Support Improved Precision Time Protocol (PTP) Timestamping Accuracy (Published)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2023<\/td>\n79<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":452492,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-452491","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/452491","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/452492"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=452491"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=452491"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=452491"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}