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BS EN 60679-1:2017

BS EN 60679-1:2017

$167.15

Piezoelectric, dielectric and electrostatic oscillators of assessed quality – Generic specification

Published By Publication Date Number of Pages
BSI 2017 42
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PDF Catalog

PDF Pages PDF Title
2 undefined
7 CONTENTS
9 FOREWORD
11 1 Scope
2 Normative references
12 3 Terms, definitions and general information
3.1 General
3.2 Terms and definitions
14 Figures
Figure 1 – Basic configurations of SAW resonators
16 Figure 2 – Example of the use of frequency offset
21 Figure 3 – Linearity of frequency modulation deviation
23 Figure 4 – Characteristics of an output waveform
24 Figure 5 – Definition of start-up time
Figure 6 – Clock signal with period jitter
25 Figure 7 – Phase jitter measures
Figure 8 – Gaussian distribution of jitter
Figure 9 – Jitter amplitude and period of jitter frequency
26 3.3 Preferred values for ratings and characteristics
3.3.1 General
Figure 10 – Jitter tolerance according to ITU-T G.825, ATIS-0900101,Telcordia GR-253 and ETSI EN 300 462
27 3.3.2 Climatic category (40/85/56)
3.3.3 Bump severity
3.3.4 Vibration severity
3.3.5 Shock severity
3.3.6 Leak rate
28 3.4 Marking
3.4.1 General
3.4.2 Packaging
4 Quality assessment procedures
4.1 General
4.2 Primary stage of manufacture
4.3 Structurally similar components
4.4 Subcontracting
29 4.5 Incorporated components
4.6 Manufacturer’s approval
4.7 Approval procedures
4.7.1 General
4.7.2 Capability approval
4.7.3 Qualification approval
30 4.8 Procedures for capability approval
4.8.1 General
4.8.2 Eligibility for capability approval
4.8.3 Application for capability approval
4.8.4 Granting of capability approval
4.8.5 Capability manual
4.9 Procedures for qualification approval
4.9.1 General
4.9.2 Eligibility for qualification approval
4.9.3 Application for qualification approval
4.9.4 Granting of qualification approval
31 4.9.5 Quality conformance inspection
4.10 Test procedures
4.11 Screening requirements
4.12 Rework and repair work
4.12.1 Rework
4.12.2 Repair work
4.13 Certified test records
4.14 Validity of release
4.15 Release for delivery
32 4.16 Unchecked parameters
33 Annex A (normative) Load circuit for logic drive
A.1 TTL and Schottky
Figure A.1 – Circuit for TTL
34 Figure A.2 – Circuit for Schottky logic
35 A.2 CMOS
A.3 ECL
Figure A.3 – Circuit for PECL
Tables
Table A.1 – Values to be used when calculating R1 and R2
36 A.4 LVDS
Figure A.4 – Circuit for LVDS
Table A.2 – Operating condition
Table A.3 – DC Electrical characteristics output load = 50 Ω to Vcc-2V
37 Annex B (normative) Latch-up test
B.1 Definition
B.1.1 Latch-up
B.1.2 Test procedure
B.2 Test method
38 Annex C (normative) Electrostatic discharge sensitivity classification
C.1 Definition
C.1.1 Electrostatic discharge (ESD)
C.1.2 Test procedure
C.2 Test methods
C.2.1 General
C.2.2 Leaded oscillator
C.2.3 SMD oscillator
C.2.4 The impact of ESD on Oscillator in steady-state
39 Annex D (normative) Digital interfaced crystal oscillator’s function
Table D.1 – Function of the digital interface
40 Bibliography

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BS EN 60679-1:2017
$167.15