BS EN 62343-4-1:2016
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Dynamic modules – Software and hardware interface. 1 x 9 wavelength selective switch
| Published By | Publication Date | Number of Pages |
| BSI | 2016 | 36 |
IEC 62343-4-1:2016 describes and provides specifications for a software and hardware interface for the 1 x 9 wavelength selective switch. These switches can be controlled by resident firmware with this interface. This standard addresses the configuration and function to control a WSS. This interface is intended to enable a user or host to retrieve the switch status and/or adjust relevant switch and attenuation settings.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 6 | CONTENTS |
| 7 | FOREWORD |
| 9 | INTRODUCTION |
| 10 | 1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions 3.2 Abbreviations |
| 11 | 4 Basic configuration of WSS interface Figures Figure 1 – Basic configuration of WSS interface |
| 12 | 5 Software interface |
| 13 | Tables Table 1 – Software interface |
| 14 | Table 2 – DPRAM memory map |
| 15 | 6 Hardware interface – Electrical connector |
| 16 | Annex A (informative) Hardware interface details Table A.1 – Connector form Table A.2 – Pin assignment |
| 17 | Table A.3 – Supply voltages and currents Table A.4 – Low voltage TTL thresholds Table A.5 – Power consumption |
| 18 | Annex B (informative) DPRAM memory map details and timing charts Table B.1 – DPRAM memory map specification A |
| 19 | Table B.2 – DPRAM memory map specification B |
| 28 | Table B.3 – Signal time specification |
| 29 | Figure B.1 – DPRAM READ CYCLE timing |
| 30 | Figure B.2 – DPRAM WRITE CYCLE timing Figure B.3 – POWER ON timing |
| 31 | Figure B.4 – START timing Figure B.5 – MASTER RESET timing |
| 32 | Figure B.6 – SOFT RESET timing Figure B.7 – DPRAM BUSY timing |
| 33 | Figure B.8 – ALARM timing |
| 34 | Bibliography |
