IEEE 1076 2002

$166.29

IEEE Standard VHDL Language Reference Manual

Published By	Publication Date	Number of Pages
IEEE	2002	309

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Description

Revision Standard – Inactive – Superseded. Replaced by 61691-1-1 Dual-logo document. Revision of the IEEE Std 1076, 2000 Edition Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.

PDF Catalog

PDF Pages	PDF Title
10	0. Overview of this standard 0.1 Intent and scope of this standard 0.2 Structure and terminology of this standard
14	1. Design entities and configurations 1.1 Entity declarations
18	1.2 Architecture bodies
21	1.3 Configuration declarations
28	2. Subprograms and packages 2.1 Subprogram declarations
31	2.2 Subprogram bodies
34	2.3 Subprogram overloading
36	2.4 Resolution functions
37	2.5 Package declarations
38	2.6 Package bodies
40	2.7 Conformance rules
42	3. Types
43	3.1 Scalar types
49	3.2 Composite types
54	3.3 Access types
57	3.4 File types
59	3.5 Protected types
64	4. Declarations 4.1 Type declarations
65	4.2 Subtype declarations
66	4.3 Objects
80	4.4 Attribute declarations
81	4.5 Component declarations 4.6 Group template declarations
82	4.7 Group declarations
84	5. Specifications 5.1 Attribute specification
86	5.2 Configuration specification
94	5.3 Disconnection specification
98	6. Names 6.1 Names
99	6.2 Simple names
100	6.3 Selected names
102	6.4 Indexed names
103	6.5 Slice names 6.6 Attribute names
106	7. Expressions 7.1 Expressions
107	7.2 Operators
115	7.3 Operands
122	7.4 Static expressions
124	7.5 Universal expressions
126	8. Sequential statements 8.1 Wait statement
128	8.2 Assertion statement
129	8.3 Report statement 8.4 Signal assignment statement
134	8.5 Variable assignment statement
135	8.6 Procedure call statement
136	8.7 If statement 8.8 Case statement
137	8.9 Loop statement
138	8.10 Next statement
139	8.11 Exit statement 8.12 Return statement 8.13 Null statement
142	9. Concurrent statements 9.1 Block statement
143	9.2 Process statement
144	9.3 Concurrent procedure call statements
145	9.4 Concurrent assertion statements
146	9.5 Concurrent signal assignment statements
151	9.6 Component instantiation statements
157	9.7 Generate statements
158	10. Scope and visibility 10.1 Declarative region
159	10.2 Scope of declarations
160	10.3 Visibility
163	10.4 Use clauses
164	10.5 The context of overload resolution
166	11. Design units and their analysis 11.1 Design units 11.2 Design libraries
167	11.3 Context clauses
168	11.4 Order of analysis
170	12. Elaboration and execution 12.1 Elaboration of a design hierarchy
172	12.2 Elaboration of a block header
173	12.3 Elaboration of a declarative part
177	12.4 Elaboration of a statement part
180	12.5 Dynamic elaboration 12.6 Execution of a model
188	13. Lexical elements 13.1 Character set
191	13.2 Lexical elements, separators, and delimiters
192	13.3 Identifiers 13.4 Abstract literals
194	13.5 Character literals 13.6 String literals
195	13.7 Bit string literals
196	13.8 Comments
197	13.9 Reserved words
198	13.10 Allowable replacements of characters
200	14. Predefined language environment 14.1 Predefined attributes
214	14.2 Package STANDARD
221	14.3 Package TEXTIO
226	Annex A (informative) Syntax summary
246	Annex B (informative) Glossary
266	Annex C (informative) Potentially nonportable constructs
268	Annex D (informative) Changes from IEEE Std 1076,2000 Edition
270	Annex E (informative) Features under consideration for removal
272	Annex F (informative) Bibliography