{"id":229147,"date":"2024-10-19T14:54:20","date_gmt":"2024-10-19T14:54:20","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62680-3-12017\/"},"modified":"2024-10-25T09:01:59","modified_gmt":"2024-10-25T09:01:59","slug":"bs-en-62680-3-12017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62680-3-12017\/","title":{"rendered":"BS EN 62680-3-1:2017"},"content":{"rendered":"

The specification is primarily targeted at peripheral developers and platform\/adapter developers, but provides valuable information for platform operating system\/BIOS\/device driver, adapter IHVs\/ISVs, and system OEMs. This specification can be used for developing new products and associated software.<\/p>\n

Product developers using this specification are expected to know and understand the USB 2.0 Specification. Specifically, USB 3.1 devices must implement device framework commands and descriptors as defined in the USB 2.0 Specification. Devices operating at the new 10 Gbps (Gen 2) speed must implement the SuperSpeedPlus enhancements defined in this version of the specification.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
2<\/td>\nundefined <\/td>\n<\/tr>\n
5<\/td>\nFOREWORD <\/td>\n<\/tr>\n
7<\/td>\nINTRODUCTION <\/td>\n<\/tr>\n
18<\/td>\nCONTENTS <\/td>\n<\/tr>\n
41<\/td>\n1 Introduction
1.1 Background
1.2 Objective of the Specification
1.3 Scope of the Document <\/td>\n<\/tr>\n
42<\/td>\n1.4 USB Product Compliance
1.5 Document Organization
1.6 Design Goals
1.7 Related Documents <\/td>\n<\/tr>\n
43<\/td>\n2 Terms and Abbreviations <\/td>\n<\/tr>\n
51<\/td>\n3 Architectural Overview
Figures
Figure 2-1 \u2013 Port and Link Pictorial <\/td>\n<\/tr>\n
52<\/td>\n3.1 USB 3.1 System Description
Figure 3-1 \u2013 USB 3.1 Dual Bus System Architecture <\/td>\n<\/tr>\n
53<\/td>\n3.1.1 USB 3.1 Physical Interface
3.1.2 USB 3.1 Power
Figure 3-2 \u2013 USB 3.1 Cable <\/td>\n<\/tr>\n
54<\/td>\n3.1.3 USB 3.1 System Configuration
3.1.4 USB 3.1 Architecture Summary
3.2 Enhanced SuperSpeed Bus Architecture
Tables
Table 3-1 \u2013 Comparing Enhanced SuperSpeed Bus to USB 2.0 Bus <\/td>\n<\/tr>\n
55<\/td>\nFigure 3-3 \u2013 USB 3.1 Terminology Reference Model <\/td>\n<\/tr>\n
56<\/td>\n3.2.1 Physical Layer
Figure 3-4 \u2013 Enhanced SuperSpeed Bus Communications Layers andPower Management Elements <\/td>\n<\/tr>\n
57<\/td>\n3.2.2 Link Layer <\/td>\n<\/tr>\n
58<\/td>\n3.2.3 Protocol Layer <\/td>\n<\/tr>\n
60<\/td>\n3.2.4 Robustness
3.2.5 Enhanced SuperSpeed Power Management <\/td>\n<\/tr>\n
61<\/td>\n3.2.6 Devices <\/td>\n<\/tr>\n
62<\/td>\nFigure 3-5 \u2013 Examples of Supported USB 3.1 USB Physical Device Topologies <\/td>\n<\/tr>\n
63<\/td>\nFigure 3-6 \u2013 SuperSpeed Only Enhanced SuperSpeed Peripheral Device Configuration
Figure 3-7 \u2013 Enhanced SuperSpeed Device Configuration <\/td>\n<\/tr>\n
65<\/td>\n3.2.7 Hosts
Figure 3-8 \u2013 Multiple SuperSpeed Bus Instances in an Enhanced SuperSpeed System <\/td>\n<\/tr>\n
66<\/td>\n3.3 Enhanced SuperSpeed Bus Data Flow Models
4 Enhanced SuperSpeed Data Flow Model
4.1 Implementer Viewpoints <\/td>\n<\/tr>\n
67<\/td>\n4.2 Enhanced SuperSpeed Communication Flow
4.2.1 Pipes
4.3 Enhanced SuperSpeed Protocol Overview
4.3.1 Differences from USB 2.0 <\/td>\n<\/tr>\n
69<\/td>\n4.4 Generalized Transfer Description <\/td>\n<\/tr>\n
70<\/td>\n4.4.1 Data Bursting
4.4.2 IN Transfers <\/td>\n<\/tr>\n
71<\/td>\n4.4.3 OUT Transfers
Figure 4-1 \u2013 Enhanced SuperSpeed IN Transaction Protocol <\/td>\n<\/tr>\n
72<\/td>\n4.4.4 Power Management and Performance
4.4.5 Control Transfers
Figure 4-2 \u2013 Enhanced SuperSpeed OUT Transaction Protocol <\/td>\n<\/tr>\n
74<\/td>\n4.4.6 Bulk Transfers <\/td>\n<\/tr>\n
75<\/td>\nFigure 4-3 \u2013 Enhanced SuperSpeed IN Stream Example <\/td>\n<\/tr>\n
77<\/td>\n4.4.7 Interrupt Transfers <\/td>\n<\/tr>\n
78<\/td>\n4.4.8 Isochronous Transfers <\/td>\n<\/tr>\n
82<\/td>\n4.4.9 Device Notifications
4.4.10 Reliability
4.4.11 Efficiency <\/td>\n<\/tr>\n
83<\/td>\n5 Mechanical
5.1 Objective
5.2 Significant Features
5.2.1 Connectors <\/td>\n<\/tr>\n
84<\/td>\nTable 5-1 \u2013 Plugs Accepted By Receptacles <\/td>\n<\/tr>\n
85<\/td>\n5.2.2 Allowed Cable Assemblies
5.2.3 Raw Cables
5.3 Connector Mating Interfaces
5.3.1 USB 3.1 Standard-A Connector <\/td>\n<\/tr>\n
88<\/td>\nFigure 5-1 \u2013 USB 3.1 Standard-A Receptacle Interface Dimensions <\/td>\n<\/tr>\n
90<\/td>\nFigure 5-2 \u2013 Example USB 3.1 Standard-A Receptacle with Grounding Springs and Required contact zones on the Standard-A Plug <\/td>\n<\/tr>\n
91<\/td>\nFigure 5-3 \u2013 Example USB 3.1 Standard-A Mid-Mount Receptacles with Insertion Detect <\/td>\n<\/tr>\n
94<\/td>\nFigure 5-4 \u2013 USB 3.1 Standard-A Plug Interface Dimensions <\/td>\n<\/tr>\n
97<\/td>\nFigure 5-5 \u2013 Example Footprint for the USB 3.1 Standard-A Receptacle \u2013 Through-Hole with Back-Shield <\/td>\n<\/tr>\n
98<\/td>\nFigure 5-6 \u2013 Example Footprint for the USB 3.1 Standard-A Receptacle \u2013 Mid-Mount Standard Mount Through-Hole with Insertion Detect <\/td>\n<\/tr>\n
99<\/td>\nFigure 5-7 \u2013 Example Footprint for the USB 3.1 Standard-A Receptacle \u2013 Mid-Mount Reverse Mount Through-Hole with Insertion Detect <\/td>\n<\/tr>\n
100<\/td>\nTable 5-2 \u2013 USB 3.1 Standard-A Connector Pin Assignments <\/td>\n<\/tr>\n
101<\/td>\n5.3.2 USB 3.1 Standard-B Connector
Figure 5-8 \u2013 Illustration of Color Coding Recommendation for USB 3.1Standard-A Connector <\/td>\n<\/tr>\n
103<\/td>\nFigure 5-9 \u2013 USB 3.1 Standard-B Receptacle Interface Dimensions <\/td>\n<\/tr>\n
104<\/td>\nFigure 5-10 \u2013 USB 3.1 Standard-B Plug Interface Dimensions <\/td>\n<\/tr>\n
105<\/td>\nFigure 5-11 \u2013 Reference Footprint for the USB 3.1 Standard-B Receptacle <\/td>\n<\/tr>\n
106<\/td>\n5.3.3 USB 3.1 Micro Connector Family
Table 5-3 \u2013 USB 3.1 Standard-B Connector Pin Assignments <\/td>\n<\/tr>\n
108<\/td>\nFigure 5-12 \u2013 USB 3.1 Micro-B and -AB Receptacles Interface Dimensions <\/td>\n<\/tr>\n
111<\/td>\nFigure 5-13 \u2013 USB 3.1 Micro-B and Micro-A Plug Interface Dimensions <\/td>\n<\/tr>\n
113<\/td>\nFigure 5-14 \u2013 Reference Footprint for the USB 3.1 Micro-B or Micro-AB Receptacle <\/td>\n<\/tr>\n
114<\/td>\n5.4 Cable Construction and Wire Assignments
5.4.1 Cable Construction
Table 5-4 \u2013 USB 3.1 Micro-B Connector Pin Assignments
Table 5-5 \u2013 USB 3.1 Micro-AB\/-A Connector Pin Assignments <\/td>\n<\/tr>\n
115<\/td>\n5.4.2 Wire Assignments
Figure 5-15 \u2013 Illustration of a USB 3.1 Cable Cross-Section <\/td>\n<\/tr>\n
116<\/td>\n5.4.3 Wire Gauges and Cable Diameters
5.5 Cable Assemblies
5.5.1 USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly
Table 5-6 \u2013 Cable Wire Assignments
Table 5-7 \u2013 Reference Wire Gauges <\/td>\n<\/tr>\n
117<\/td>\nFigure 5-16 \u2013 USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly <\/td>\n<\/tr>\n
118<\/td>\n5.5.2 USB 3.1 Standard-A to USB 3.1 Standard-A Cable Assembly
5.5.3 USB 3.1 Standard-A to USB 3.1 Micro-B Cable Assembly
Table 5-8 \u2013 USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly Wiring
Table 5-9 \u2013 USB 3.1 Standard-A to USB 3.1 Standard-A Cable Assembly Wiring <\/td>\n<\/tr>\n
119<\/td>\nFigure 5-17 \u2013 USB 3.1 Micro-B Plug Cable Overmold Dimensions <\/td>\n<\/tr>\n
120<\/td>\n5.5.4 USB 3.1 Micro-A to USB 3.1 Micro-B Cable Assembly
Table 5-10 \u2013 USB 3.1 Standard-A to USB 3.1 Micro-B Cable Assembly Wiring <\/td>\n<\/tr>\n
121<\/td>\nFigure 5-18 \u2013 USB 3.1 Micro-A Cable Overmold Dimensions <\/td>\n<\/tr>\n
122<\/td>\n5.5.5 USB 3.1 Micro-A to USB 3.1 Standard-B Cable Assembly
Table 5-11 \u2013 USB 3.1 Micro-A to USB 3.1 Micro-B Cable Assembly Wiring
Table 5-12 \u2013 USB 3.1 Micro-A to USB 3.1 Standard-B Cable Assembly Wiring <\/td>\n<\/tr>\n
123<\/td>\n5.5.6 USB 3.1 Icon Location
5.5.7 Cable Assembly Length
5.6 Electrical Requirements
Figure 5-19 \u2013 Typical Plug Orientation <\/td>\n<\/tr>\n
124<\/td>\n5.6.1 Enhanced SuperSpeed Electrical Requirements <\/td>\n<\/tr>\n
125<\/td>\nFigure 5-20 \u2013 Recommended Ground Void Dimension for USB Standard-A Receptacle
Table 5-13 \u2013 SDP Differential Insertion Loss Examples for Gen 2 speed
Table 5-14 \u2013 SDP Differential Insertion Loss Examples for Gen 2 speed with Coaxial Construction <\/td>\n<\/tr>\n
126<\/td>\nFigure 5-21 \u2013 Impedance Limits of a Mated Connector for Gen 2 Speed <\/td>\n<\/tr>\n
127<\/td>\nFigure 5-22 \u2013 Illustration of Cable Assembly Mounted on Test Fixture
Figure 5-23 \u2013 Illustration of Cable Assembly with Reference Host and Device
Table 5-15 \u2013 Design Targets <\/td>\n<\/tr>\n
128<\/td>\nFigure 5-24 \u2013 Illustration of Insertion Loss Fit at Nyquist Frequency <\/td>\n<\/tr>\n
129<\/td>\nFigure 5-25 \u2013 Example of Insertion Loss Deviation <\/td>\n<\/tr>\n
131<\/td>\nFigure 5-26 \u2013 Pass\/Fail Examples <\/td>\n<\/tr>\n
132<\/td>\nFigure 5-27 \u2013 Illustration of Peak-to-Peak Crosstalk
Figure 5-28 \u2013 Differential-to-Common-Mode Conversion Requirement for Gen 2 <\/td>\n<\/tr>\n
133<\/td>\n5.6.2 DC Electrical Requirements
5.7 Mechanical and Environmental Requirements
Figure 5-29 \u2013 Set Up For Cable SE Measurement (subject to change) <\/td>\n<\/tr>\n
134<\/td>\n5.7.1 Mechanical Requirements
Table 5-16 \u2013 Durability Ratings <\/td>\n<\/tr>\n
136<\/td>\nFigure 5-30 \u2013 4-Axes Continuity Test <\/td>\n<\/tr>\n
137<\/td>\n5.7.2 Environmental Requirements
5.7.3 Materials
Table 5-17 \u2013 Environmental Test Conditions <\/td>\n<\/tr>\n
138<\/td>\n5.8 Implementation Notes and Design Guides
5.8.1 Mated Connector Dimensions
Table 5-18 \u2013 Reference Materials <\/td>\n<\/tr>\n
139<\/td>\nFigure 5-31 \u2013 Mated USB 3.1 Standard-A Connector
Figure 5-32 \u2013 Mated USB 3.1 Standard-B Connector <\/td>\n<\/tr>\n
140<\/td>\n5.8.2 EMI and RFI Management
Figure 5-33 \u2013 Mated USB 3.1 Micro-B Connector <\/td>\n<\/tr>\n
141<\/td>\n5.8.3 Stacked Connectors
Figure 5-34 \u2013 Examples of Connector Apertures <\/td>\n<\/tr>\n
142<\/td>\n6 Physical Layer
6.1 Physical Layer Overview
6.2 Physical Layer Functions
Figure 6-1 \u2013 SuperSpeed Physical Layer <\/td>\n<\/tr>\n
143<\/td>\nFigure 6-2 \u2013 Transmitter Block Diagram <\/td>\n<\/tr>\n
144<\/td>\nFigure 6-3 \u2013 Gen 1 Receiver Block Diagram <\/td>\n<\/tr>\n
145<\/td>\nFigure 6-4 \u2013 Gen 2 Receiver Block Diagram <\/td>\n<\/tr>\n
146<\/td>\n6.2.1 Measurement Overview
6.2.2 Channel Overview
Figure 6-5 \u2013 Channel Models <\/td>\n<\/tr>\n
147<\/td>\n6.3 Symbol Encoding
6.3.1 Gen 1 Encoding
Figure 6-6 \u2013 Character to Symbol Mapping
Figure 6-7 \u2013 Bit Transmission Order <\/td>\n<\/tr>\n
148<\/td>\nFigure 6-8 \u2013 LFSR with Scrambling Polynomial <\/td>\n<\/tr>\n
149<\/td>\n6.3.2 Gen 2 Encoding
Figure 6-9 \u2013 Gen 2 Serialization and Deserialization Order <\/td>\n<\/tr>\n
150<\/td>\nFigure 6-10 \u2013 Gen 2 Bit Transmission Order and Framing <\/td>\n<\/tr>\n
152<\/td>\nFigure 6-11 \u2013 LFSR for use in Gen 2 operation <\/td>\n<\/tr>\n
153<\/td>\n6.3.3 Special Symbols for Framing and Link Management
Table 6-1 \u2013 Special Symbols <\/td>\n<\/tr>\n
154<\/td>\n6.4 Link Initialization and Training
6.4.1 Link Training <\/td>\n<\/tr>\n
155<\/td>\nTable 6-2 \u2013 Gen 1 TSEQ Ordered Set
Table 6-3 \u2013 Gen 1 TS1 Ordered Set
Table 6-4 \u2013 Gen 1 TS2 Ordered Set <\/td>\n<\/tr>\n
156<\/td>\nTable 6-5 \u2013 Gen 1\/Gen 2 Link Configuration <\/td>\n<\/tr>\n
157<\/td>\nTable 6-6 \u2013 Gen 2 TS1 Ordered Set <\/td>\n<\/tr>\n
158<\/td>\nTable 6-7 \u2013 Gen 2 TS2 Ordered Set
Table 6-8 \u2013 Gen 2 TSEQ Ordered Set
Table 6-9 \u2013 Gen 2 SYNC Ordered Set
Table 6-10 \u2013 SDS Ordered Set <\/td>\n<\/tr>\n
159<\/td>\n6.4.2 Lane Polarity Inversion
6.4.3 Elasticity Buffer and SKP Ordered Set <\/td>\n<\/tr>\n
160<\/td>\nTable 6-11 \u2013 Gen 1 SKP Ordered Set Structure <\/td>\n<\/tr>\n
161<\/td>\n6.4.4 Compliance Pattern
Table 6-12 \u2013 Gen 2 SKP Ordered Set <\/td>\n<\/tr>\n
162<\/td>\n6.5 Clock and Jitter
6.5.1 Informative Jitter Budgeting
Table 6-13 \u2013 Compliance Pattern Sequences
Table 6-14 \u2013 Gen 2 Compliance Pattern <\/td>\n<\/tr>\n
163<\/td>\n6.5.2 Normative Clock Recovery Function
Figure 6-12 \u2013 Jitter Filtering \u2013 \u201cGolden PLL\u201d and Jitter Transfer Functions
Table 6-15 \u2013 Informative Jitter Budgeting at the Silicon Pads <\/td>\n<\/tr>\n
164<\/td>\nFigure 6-13 \u2013 \u201cGolden PLL\u201d and Jitter Transfer Functions for Gen 1 Operation
Figure 6-14 \u2013 \u201cGolden PLL\u201d and Jitter Transfer Functions for Gen 2 Operation <\/td>\n<\/tr>\n
165<\/td>\n6.5.3 Normative Spread Spectrum Clocking (SSC)
Figure 6-15 \u2013 Example of Period Modulation from Triangular SSC
Table 6-16 \u2013 SSC Parameters <\/td>\n<\/tr>\n
166<\/td>\n6.5.4 Normative Slew Rate Limit
6.6 Signaling
6.6.1 Eye Diagrams <\/td>\n<\/tr>\n
167<\/td>\n6.6.2 Voltage Level Definitions
Figure 6-16 \u2013 Eye Masks <\/td>\n<\/tr>\n
168<\/td>\n6.6.3 Tx and Rx Input Parasitics
6.7 Transmitter Specifications
6.7.1 Transmitter Electrical Parameters
Figure 6-17 \u2013 Single-ended and Differential Voltage Levels
Figure 6-18 \u2013 Device Termination Schematic <\/td>\n<\/tr>\n
169<\/td>\nTable 6-17 \u2013 Transmitter Normative Electrical Parameters <\/td>\n<\/tr>\n
170<\/td>\n6.7.2 Low Power Transmitter
6.7.3 Transmitter Eye
Table 6-18 \u2013 Transmitter Informative Electrical Parameters at Silicon Pads <\/td>\n<\/tr>\n
171<\/td>\n6.7.4 Tx Compliance Reference Receiver Equalize Function
6.7.5 Informative Transmitter De-emphasis
Figure 6-19 \u2013 Tx Normative Setup with Reference Channel
Table 6-19 \u2013 Normative Transmitter Eye Mask at Test Point TP1 <\/td>\n<\/tr>\n
172<\/td>\nFigure 6-20 \u2013 De-Emphasis Waveform
Figure 6-21 \u2013 3-tap Transmit Equalizer Structure <\/td>\n<\/tr>\n
173<\/td>\n6.7.6 Entry into Electrical Idle, U1
6.8 Receiver Specifications
6.8.1 Receiver Equalization Training
Figure 6-22 \u2013 Example Output Waveform for 3-tap Transmit Equalizer
Table 6-20 \u2013 Informative Gen 2 Transmitter Equalization Settings <\/td>\n<\/tr>\n
174<\/td>\n6.8.2 Informative Receiver CTLE Function
Figure 6-23 \u2013 Frequency Spectrum of TSEQ <\/td>\n<\/tr>\n
175<\/td>\nFigure 6-24 \u2013 Gen 1 Tx Compliance Rx EQ Transfer Function <\/td>\n<\/tr>\n
176<\/td>\nFigure 6-25 \u2013 Gen 2 Compliance Rx EQ Transfer Function <\/td>\n<\/tr>\n
177<\/td>\n6.8.3 Receiver Electrical Parameters
Figure 6-26 \u2013 Gen 2 reference DFE Function
Table 6-21 \u2013 Receiver Normative Electrical Parameters <\/td>\n<\/tr>\n
178<\/td>\n6.8.4 Receiver Loopback
Table 6-22 \u2013 Receiver Informative Electrical Parameters <\/td>\n<\/tr>\n
179<\/td>\n6.8.5 Normative Receiver Tolerance Compliance Test
Table 6-23 \u2013 BRST
Table 6-24 \u2013 BDAT
Table 6-25 \u2013 BERC
Table 6-26 \u2013 BCNT <\/td>\n<\/tr>\n
180<\/td>\nFigure 6-27 \u2013 Rx Tolerance Setup
Figure 6-28 \u2013 Jitter Tolerance Curve <\/td>\n<\/tr>\n
181<\/td>\n6.9 Low Frequency Periodic Signaling (LFPS)
6.9.1 LFPS Signal Definition
Table 6-27 \u2013 Input Jitter Requirements for Rx Tolerance Testing <\/td>\n<\/tr>\n
182<\/td>\nFigure 6-29 \u2013 LFPS Signaling
Table 6-28 \u2013 Normative LFPS Electrical Specification <\/td>\n<\/tr>\n
183<\/td>\n6.9.2 Example LFPS Handshake for U1\/U2 Exit, Loopback Exit, and U3 Wakeup
Table 6-29 \u2013 LFPS Transmitter Timing for SuperSpeed Designs1 <\/td>\n<\/tr>\n
184<\/td>\nFigure 6-30 \u2013 U1 Exit, U2 Exit, and U3 Wakeup LFPS Handshake Timing Diagram <\/td>\n<\/tr>\n
185<\/td>\n6.9.3 Warm Reset
Table 6-30 \u2013 LFPS Handshake Timing for U1\/U2 Exit, Loopback Exit, and U3 Wakeup <\/td>\n<\/tr>\n
186<\/td>\n6.9.4 SuperSpeedPlus Capability Declaration
Figure 6-31 \u2013 Example of Warm Reset Out of U3
Figure 6-32 \u2013 Example of Binary Representation based on Polling.LFPS
Table 6-31 \u2013 Binary Representation of Polling.LFPS <\/td>\n<\/tr>\n
187<\/td>\n6.9.5 SuperSpeedPlus LFPS Based PWM Message (LBPM)
Figure 6-33 \u2013 SCD1\/SCD2 transmission <\/td>\n<\/tr>\n
188<\/td>\nFigure 6-34 \u2013 Logic Representation of LBPS
Table 6-32 \u2013 LBPS Transmit and Receive Specification <\/td>\n<\/tr>\n
189<\/td>\n6.10 Transmitter and Receiver DC Specifications
6.10.1 Informative ESD Protection
6.10.2 Informative Short Circuit Requirements
6.10.3 Normative High Impedance Reflections
6.11 Receiver Detection
6.11.1 Rx Detect Overview
Figure 6-35 \u2013 LBPM Transmission Examples <\/td>\n<\/tr>\n
190<\/td>\n6.11.2 Rx Detect Sequence
6.11.3 Upper Limit on Channel Capacitance
Figure 6-36 \u2013 Rx Detect Schematic <\/td>\n<\/tr>\n
191<\/td>\n6.12 Retimers
7 Link Layer
Figure 7-1 \u2013 Link Layer <\/td>\n<\/tr>\n
192<\/td>\n7.1 Byte Ordering
7.1.1 SuperSpeed USB Line Code
7.1.2 SuperSpeedPlus USB Line Code
7.2 Link Management and Flow Control
Figure 7-2 \u2013 Byte Ordering <\/td>\n<\/tr>\n
193<\/td>\n7.2.1 Packets and Packet Framing
Figure 7-3 \u2013 Enhanced SuperSpeed Header Packet with HPSTART, Packet Header, and Link Control Word <\/td>\n<\/tr>\n
194<\/td>\nFigure 7-4 \u2013 SuperSpeedPlus DPH Format
Figure 7-5 \u2013 Packet Header <\/td>\n<\/tr>\n
195<\/td>\nFigure 7-6 \u2013 CRC-16 Remainder Generation
Table 7-1 \u2013 CRC-16 Mapping <\/td>\n<\/tr>\n
196<\/td>\nFigure 7-7 \u2013 Link Control Word
Figure 7-8 \u2013 CRC-5 Remainder Generation <\/td>\n<\/tr>\n
197<\/td>\nFigure 7-9 \u2013 Data Packet Payload with CRC-32 and Framing <\/td>\n<\/tr>\n
198<\/td>\nFigure 7-10 \u2013 CRC-32 Remainder Generation <\/td>\n<\/tr>\n
199<\/td>\nTable 7-2 \u2013 CRC-32 Mapping <\/td>\n<\/tr>\n
200<\/td>\nFigure 7-11 \u2013 Data Packet with Data Packet Header Followed byData Packet Payload. (a) SuperSpeed DP; (b). SuperSpeedPlus DP <\/td>\n<\/tr>\n
201<\/td>\n7.2.2 Link Commands
Figure 7-12 \u2013 Link Command Structure
Figure 7-13 \u2013 Link Command Word Structure
Table 7-3 \u2013 Link Command Ordered Set Structure <\/td>\n<\/tr>\n
202<\/td>\nTable 7-4 \u2013 Link Command Bit Definitions <\/td>\n<\/tr>\n
204<\/td>\nTable 7-5 \u2013 Link Command Definitions <\/td>\n<\/tr>\n
205<\/td>\n7.2.3 Logical Idle
7.2.4 Link Command Usage for Flow Control, Error Recovery, and Power Management
Table 7-6 \u2013 Logical Idle Definition <\/td>\n<\/tr>\n
216<\/td>\nTable 7-7 \u2013 Transmitter Timers Summary <\/td>\n<\/tr>\n
217<\/td>\nTable 7-8 \u2013 Link Flow Control Timers Summary <\/td>\n<\/tr>\n
221<\/td>\n7.3 Link Error Rules\/Recovery
7.3.1 Overview of Enhanced SuperSpeed Bit Errors
7.3.2 Link Error Types, Detection, and Recovery
7.3.3 Link Error Statistics <\/td>\n<\/tr>\n
222<\/td>\n7.3.4 Header Packet Errors <\/td>\n<\/tr>\n
223<\/td>\n7.3.5 Link Command Errors
Table 7-9 \u2013 Valid Packet Framing Symbol Order (Sx is One of SHP, DPHP, SDP, END or EDB) <\/td>\n<\/tr>\n
224<\/td>\n7.3.6 ACK Tx Header Sequence Number Error
Table 7-10 \u2013 Valid Link Command Symbol Order <\/td>\n<\/tr>\n
225<\/td>\n7.3.7 Header Sequence Number Advertisement Error
7.3.8 SuperSpeed Rx Header Buffer Credit Advertisement Error <\/td>\n<\/tr>\n
226<\/td>\n7.3.9 SuperSpeedPlus Type 1\/Type 2 Rx Buffer Credit Advertisement Error
7.3.10 Training Sequence Error <\/td>\n<\/tr>\n
227<\/td>\n7.3.11 SuperSpeed 8b\/10b Errors
7.3.12 SuperSpeedPlus Block Header Errors
7.3.13 Summary of Error Types and Recovery <\/td>\n<\/tr>\n
228<\/td>\nTable 7-11 \u2013 Error Types and Recovery <\/td>\n<\/tr>\n
229<\/td>\n7.4 PowerOn Reset and Inband Reset
7.4.1 PowerOn Reset <\/td>\n<\/tr>\n
230<\/td>\n7.4.2 Inband Reset <\/td>\n<\/tr>\n
231<\/td>\n7.5 Link Training and Status State Machine (LTSSM) <\/td>\n<\/tr>\n
232<\/td>\nTable 7-12 \u2013 LTSSM State Transition Timeouts <\/td>\n<\/tr>\n
233<\/td>\n7.5.1 eSS.Disabled
Figure 7-14 \u2013 State Diagram of the Link Training and Status State Machine <\/td>\n<\/tr>\n
235<\/td>\n7.5.2 eSS.Inactive
Figure 7-15 \u2013 eSS.Disabled Substate Machine <\/td>\n<\/tr>\n
236<\/td>\n7.5.3 Rx.Detect
Figure 7-16 \u2013 eSS.Inactive Substate Machine <\/td>\n<\/tr>\n
239<\/td>\n7.5.4 Polling
Figure 7-17 \u2013 Rx.Detect Substate Machine <\/td>\n<\/tr>\n
243<\/td>\nTable 7-13 \u2013 PHY Capability LBPM <\/td>\n<\/tr>\n
250<\/td>\n7.5.5 Compliance Mode
Figure 7-18 \u2013 Polling Substate Machine <\/td>\n<\/tr>\n
251<\/td>\n7.5.6 U0 <\/td>\n<\/tr>\n
252<\/td>\n7.5.7 U1 <\/td>\n<\/tr>\n
253<\/td>\n7.5.8 U2
Figure 7-19 \u2013 U1 <\/td>\n<\/tr>\n
254<\/td>\n7.5.9 U3
Figure 7-20 \u2013 U2 <\/td>\n<\/tr>\n
255<\/td>\n7.5.10 Recovery
Figure 7-21 \u2013 U3 <\/td>\n<\/tr>\n
259<\/td>\n7.5.11 Loopback
Figure 7-22 \u2013 Recovery Substate Machine <\/td>\n<\/tr>\n
261<\/td>\n7.5.12 Hot Reset
Figure 7-23 \u2013 Loopback Substate Machine <\/td>\n<\/tr>\n
263<\/td>\n8 Protocol Layer
Figure 7-24 \u2013 Hot Reset Substate Machine <\/td>\n<\/tr>\n
264<\/td>\n8.1 Enhanced SuperSpeed Transactions
8.1.1 Transactions on a SuperSpeed Bus Instance
Figure 8-1 \u2013 Protocol Layer Highlighted <\/td>\n<\/tr>\n
265<\/td>\n8.1.2 Transactions on a SuperSpeedPlus Bus Instance <\/td>\n<\/tr>\n
266<\/td>\n8.2 Packet Types
8.3 Packet Formats
8.3.1 Fields Common to all Headers
Figure 8-2 \u2013 Example Transaction Packet <\/td>\n<\/tr>\n
267<\/td>\nFigure 8-3 \u2013 Link Control Word Detail
Table 8-1 \u2013 Type Field Description <\/td>\n<\/tr>\n
268<\/td>\n8.4 Link Management Packet (LMP)
8.4.1 Subtype Field
Figure 8-4 \u2013 Link Management Packet Structure
Table 8-2 \u2013 Link Control Word Format <\/td>\n<\/tr>\n
269<\/td>\n8.4.2 Set Link Function
Figure 8-5 \u2013 Set Link Function LMP
Table 8-3 \u2013 Link Management Packet Subtype Field <\/td>\n<\/tr>\n
270<\/td>\n8.4.3 U2 Inactivity Timeout
8.4.4 Vendor Device Test
Figure 8-6 \u2013 U2 Inactivity Timeout LMP
Figure 8-7 \u2013 Vendor Device Test LMP
Table 8-4 \u2013 Set Link Function
Table 8-5 \u2013 U2 Inactivity Timer Functionality <\/td>\n<\/tr>\n
271<\/td>\n8.4.5 Port Capabilities
Figure 8-8 \u2013 Port Capability LMP
Table 8-6 \u2013 Vendor-specific Device Test Function <\/td>\n<\/tr>\n
272<\/td>\nTable 8-7 \u2013 Port Capability LMP Format
Table 8-8 \u2013 Port Type Selection Matrix <\/td>\n<\/tr>\n
273<\/td>\n8.4.6 Port Configuration
8.4.7 Port Configuration Response
Figure 8-9 \u2013 Port Configuration LMP
Table 8-9 \u2013 Port Configuration LMP Format (Differences with Port Capability LMP) <\/td>\n<\/tr>\n
274<\/td>\n8.4.8 Precision Time Measurement
Figure 8-10 \u2013 Port Configuration Response LMP
Table 8-10 \u2013 Port Configuration Response LMP Format (Differences with Port Capability LMP) <\/td>\n<\/tr>\n
275<\/td>\nFigure 8-11 \u2013 Link Delay Measurement Protocol <\/td>\n<\/tr>\n
276<\/td>\nFigure 8-12 \u2013 PTM ITP Protocol <\/td>\n<\/tr>\n
277<\/td>\nFigure 8-13 \u2013 LDM State Machine Notation <\/td>\n<\/tr>\n
278<\/td>\nFigure 8-14 \u2013 LDM Requester State Machine <\/td>\n<\/tr>\n
280<\/td>\nFigure 8-15 \u2013 LDM Responder State Machine <\/td>\n<\/tr>\n
284<\/td>\nFigure 8-16 \u2013 PTM Path Performance Contributors <\/td>\n<\/tr>\n
286<\/td>\nFigure 8-17 \u2013 LDM LMP <\/td>\n<\/tr>\n
287<\/td>\n8.5 Transaction Packet (TP)
8.5.1 Acknowledgement (ACK) Transaction Packet
Table 8-11 \u2013 LDM LMP
Table 8-12 \u2013 Transaction Packet Subtype Field <\/td>\n<\/tr>\n
288<\/td>\nFigure 8-18 \u2013 ACK Transaction Packet <\/td>\n<\/tr>\n
289<\/td>\nTable 8-13 \u2013 ACK TP Format <\/td>\n<\/tr>\n
290<\/td>\n8.5.2 Not Ready (NRDY) Transaction Packet <\/td>\n<\/tr>\n
291<\/td>\n8.5.3 Endpoint Ready (ERDY) Transaction Packet
Figure 8-19 \u2013 NRDY Transaction Packet
Figure 8-20 \u2013 ERDY Transaction Packet
Table 8-14 \u2013 NRDY TP Format (Differences with ACK TP)
Table 8-15 \u2013 ERDY TP Format (Differences with ACK TP) <\/td>\n<\/tr>\n
292<\/td>\n8.5.4 STATUS Transaction Packet
8.5.5 STALL Transaction Packet
8.5.6 Device Notification (DEV_NOTIFICATION) Transaction Packet
Figure 8-21 \u2013 STATUS Transaction Packet
Figure 8-22 \u2013 STALL Transaction Packet
Table 8-16 \u2013 STATUS TP Format (Differences with ACK TP)
Table 8-17 \u2013 STALL TP Format (Differences with ACK TP) <\/td>\n<\/tr>\n
293<\/td>\nFigure 8-23 \u2013 Device Notification Transaction Packet
Figure 8-24 \u2013 Function Wake Device Notification
Table 8-18 \u2013 Device Notification TP Format (Differences with ACK TP) <\/td>\n<\/tr>\n
294<\/td>\nFigure 8-25 \u2013 Latency Tolerance Message Device Notification
Table 8-19 \u2013 Function Wake Device Notification
Table 8-20 \u2013 Latency Tolerance Message Device Notification <\/td>\n<\/tr>\n
295<\/td>\nFigure 8-26 \u2013 Bus Interval Adjustment Message Device Notification
Table 8-21 \u2013 Bus Interval Adjustment Message Device Notification <\/td>\n<\/tr>\n
298<\/td>\nFigure 8-27 \u2013 Sublink Speed Device Notification
Table 8-22 \u2013 Sublink Speed Device Notification <\/td>\n<\/tr>\n
299<\/td>\n8.5.7 PING Transaction Packet
8.5.8 PING_RESPONSE Transaction Packet
Figure 8-28 \u2013 PING Transaction Packet
Table 8-23 \u2013 PING TP Format (differences with ACK TP) <\/td>\n<\/tr>\n
300<\/td>\n8.6 Data Packet (DP)
Figure 8-29 \u2013 PING_RESPONSE Transaction Packet
Figure 8-30 \u2013 Example Data Packet
Table 8-24 \u2013 PING_RESPONSE TP Format (Differences with ACK TP) <\/td>\n<\/tr>\n
301<\/td>\nTable 8-25 \u2013 Data Packet Format (Differences with ACK TP) <\/td>\n<\/tr>\n
302<\/td>\n8.7 Isochronous Timestamp Packet (ITP)
Figure 8-31 \u2013 Isochronous Timestamp Packet
Table 8-26 \u2013 Isochronous Timestamp Packet Format <\/td>\n<\/tr>\n
303<\/td>\n8.8 Addressing Triple
8.9 Route String Field
8.9.1 Route String Port Field
8.9.2 Route String Port Field Width
8.9.3 Port Number
8.10 Transaction Packet Usages
Figure 8-32 \u2013 Route String Detail <\/td>\n<\/tr>\n
304<\/td>\n8.10.1 Flow Control Conditions
8.10.2 Burst Transactions <\/td>\n<\/tr>\n
306<\/td>\n8.10.3 Short Packets
8.10.4 SuperSpeedPlus Transaction Reordering <\/td>\n<\/tr>\n
307<\/td>\nFigure 8-33 \u2013 Sample Concurrent BULK IN Transactions <\/td>\n<\/tr>\n
308<\/td>\n8.11 TP or DP Responses
Figure 8-34 \u2013 Sample Concurrent BULK and Isochronous IN Transactions <\/td>\n<\/tr>\n
309<\/td>\n8.11.1 Device Response to TP Requesting Data
8.11.2 Host Response to Data Received from a Device
Table 8-27 \u2013 Device Responses to TP Requesting Data (Bulk, Control, and Interrupt Endpoints) <\/td>\n<\/tr>\n
310<\/td>\n8.11.3 Device Response to Data Received from the Host
Table 8-28 \u2013 Host Responses to Data Received from a Device (Bulk, Control, and Interrupt Endpoints) <\/td>\n<\/tr>\n
311<\/td>\n8.11.4 Device Response to a SETUP DP
Table 8-29 \u2013 Device Responses to OUT Transactions (Bulk, Control, and Interrupt Endpoints) <\/td>\n<\/tr>\n
312<\/td>\n8.12 TP Sequences
8.12.1 Bulk Transactions
Table 8-30 \u2013 Device Responses to SETUP Transactions (Only for Control Endpoints) <\/td>\n<\/tr>\n
313<\/td>\nFigure 8-35 \u2013 Legend for State Machines <\/td>\n<\/tr>\n
315<\/td>\nFigure 8-36 \u2013 Sample BULK IN Sequence <\/td>\n<\/tr>\n
316<\/td>\nFigure 8-37 \u2013 Sample BULK OUT Sequence <\/td>\n<\/tr>\n
317<\/td>\nFigure 8-38 \u2013 General Stream Protocol State Machine (SPSM) <\/td>\n<\/tr>\n
320<\/td>\nFigure 8-39 \u2013 Device IN Stream Protocol State Machine (DISPSM) <\/td>\n<\/tr>\n
323<\/td>\nFigure 8-40 \u2013 Device IN Move Data State Machine (DIMDSM) <\/td>\n<\/tr>\n
325<\/td>\nFigure 8-41 \u2013 Device OUT Stream Protocol State Machine (DOSPSM) <\/td>\n<\/tr>\n
328<\/td>\nFigure 8-42 \u2013 Device OUT Move Data State Machine (DOMDSM) <\/td>\n<\/tr>\n
331<\/td>\nFigure 8-43 \u2013 Host IN Stream Protocol State Machine (HISPSM) <\/td>\n<\/tr>\n
333<\/td>\nFigure 8-44 \u2013 Host IN Move Data State Machine (HIMDSM) <\/td>\n<\/tr>\n
336<\/td>\nFigure 8-45 \u2013 Host OUT Stream Protocol State Machine (HOSPSM) <\/td>\n<\/tr>\n
339<\/td>\nFigure 8-46 \u2013 Host OUT Move Data State Machine (HOMDSM) <\/td>\n<\/tr>\n
341<\/td>\n8.12.2 Control Transfers <\/td>\n<\/tr>\n
342<\/td>\nFigure 8-47 \u2013 Control Read Sequence <\/td>\n<\/tr>\n
343<\/td>\nFigure 8-48 \u2013 Control Write Sequence <\/td>\n<\/tr>\n
344<\/td>\n8.12.3 Bus Interval and Service Interval
8.12.4 Interrupt Transactions
Table 8-31 \u2013 Status Stage Responses <\/td>\n<\/tr>\n
346<\/td>\nFigure 8-49 \u2013 Host Sends Interrupt IN Transaction in Each Service Interval
Figure 8-50 \u2013 Host Stops Servicing Interrupt IN Transaction Once NRDY is Received <\/td>\n<\/tr>\n
347<\/td>\nFigure 8-51 \u2013 Host Resumes IN Transaction after Device Sent ERDY
Figure 8-52 \u2013 Endpoint Sends STALL TP
Figure 8-53 \u2013 Host Detects Error in Data and Device Resends Data <\/td>\n<\/tr>\n
349<\/td>\nFigure 8-54 \u2013 Host Sends Interrupt OUT Transaction in Each Service Interval
Figure 8-55 \u2013 Host Stops Servicing Interrupt OUT Transaction Once NRDY is Received
Figure 8-56 \u2013 Host Resumes Sending Interrupt OUT Transaction After Device Sent ERDY <\/td>\n<\/tr>\n
350<\/td>\n8.12.5 Host Timing Information
Figure 8-57 \u2013 Device Detects Error in Data and Host Resends Data
Figure 8-58 \u2013 Endpoint Sends STALL TP <\/td>\n<\/tr>\n
351<\/td>\n8.12.6 Isochronous Transactions
Figure 8-59 \u2013 Multiple Active Isochronous Endpoints withAligned Service Interval Boundaries <\/td>\n<\/tr>\n
352<\/td>\nFigure 8-60 \u2013 Enhanced SuperSpeed Isochronous IN Transaction Format
Figure 8-61 \u2013 Enhanced SuperSpeed Isochronous OUT Transaction Format <\/td>\n<\/tr>\n
353<\/td>\nFigure 8-62 \u2013 Sample Enhanced SuperSpeed Isochronous IN Transaction <\/td>\n<\/tr>\n
354<\/td>\nFigure 8-63 \u2013 Sample Enhanced SuperSpeed Isochronous OUT Transaction <\/td>\n<\/tr>\n
355<\/td>\nFigure 8-64 \u2013 Sample Enhanced SuperSpeed Isochronous IN Transaction <\/td>\n<\/tr>\n
356<\/td>\nFigure 8-65 \u2013 Sample Enhanced SuperSpeed Isochronous OUT Transaction <\/td>\n<\/tr>\n
358<\/td>\nFigure 8-66 \u2013 Sample Smart Enhanced SuperSpeed Isochronous IN Transaction <\/td>\n<\/tr>\n
359<\/td>\nFigure 8-67 \u2013 Sample Smart Enhanced SuperSpeed Isochronous OUT Transaction <\/td>\n<\/tr>\n
360<\/td>\nTable 8-32 \u2013 ACK TP and DPs for Pipelined Isochronous IN Transactions <\/td>\n<\/tr>\n
361<\/td>\nFigure 8-68 \u2013 Sample Pipeline Isochronous IN Transactions <\/td>\n<\/tr>\n
362<\/td>\nTable 8-33 \u2013 Device Responses to Isochronous IN Transactions <\/td>\n<\/tr>\n
363<\/td>\n8.13 Timing Parameters
Table 8-34 \u2013 Host Responses to IN Transactions
Table 8-35 \u2013 Device Responses to OUT Data Packets <\/td>\n<\/tr>\n
364<\/td>\nTable 8-36 \u2013 Timing Parameters <\/td>\n<\/tr>\n
366<\/td>\n9 Device Framework
9.1 USB Device States
9.1.1 Visible Device States <\/td>\n<\/tr>\n
367<\/td>\nFigure 9-1 \u2013 Peripheral State Diagram and Hub State Diagram (Enhanced SuperSpeed Portion Only) <\/td>\n<\/tr>\n
368<\/td>\nTable 9-1 \u2013 Visible Enhanced SuperSpeed Device States <\/td>\n<\/tr>\n
371<\/td>\n9.1.2 Bus Enumeration <\/td>\n<\/tr>\n
372<\/td>\n9.2 Generic Device Operations
9.2.1 Dynamic Attachment and Removal
9.2.2 Address Assignment
9.2.3 Configuration <\/td>\n<\/tr>\n
373<\/td>\n9.2.4 Data Transfer
9.2.5 Power Management <\/td>\n<\/tr>\n
374<\/td>\nTable 9-2 \u2013 Preserved USB Suspend State Parameters <\/td>\n<\/tr>\n
375<\/td>\n9.2.6 Request Processing <\/td>\n<\/tr>\n
377<\/td>\n9.2.7 Request Error
9.3 USB Device Requests
9.3.1 bmRequestType
Table 9-3 \u2013 Format of Setup Data <\/td>\n<\/tr>\n
378<\/td>\n9.3.2 bRequest
9.3.3 wValue
9.3.4 wIndex
9.3.5 wLength
Figure 9-2 \u2013 wIndex Format when Specifying an Endpoint
Figure 9-3 \u2013 wIndex Format when Specifying an Interface <\/td>\n<\/tr>\n
379<\/td>\n9.4 Standard Device Requests
Table 9-4 \u2013 Standard Device Requests <\/td>\n<\/tr>\n
380<\/td>\nTable 9-5 \u2013 Standard Request Codes <\/td>\n<\/tr>\n
381<\/td>\nTable 9-6 \u2013 Descriptor Types
Table 9-7 \u2013 Standard Feature Selectors <\/td>\n<\/tr>\n
382<\/td>\n9.4.1 Clear Feature
9.4.2 Get Configuration <\/td>\n<\/tr>\n
383<\/td>\n9.4.3 Get Descriptor <\/td>\n<\/tr>\n
384<\/td>\n9.4.4 Get Interface
9.4.5 Get Status <\/td>\n<\/tr>\n
385<\/td>\nFigure 9-4 \u2013 Information Returned by a Standard GetStatus() Request to a Device
Table 9-8 \u2013 Standard Status Type Codes <\/td>\n<\/tr>\n
386<\/td>\nFigure 9-5 \u2013 Information Returned by a Standard GetStatus() Request to an Interface
Figure 9-6 \u2013 Information Returned by a Standard GetStatus() Request to an Endpoint <\/td>\n<\/tr>\n
387<\/td>\n9.4.6 Set Address
Figure 9-7 \u2013 Information Returned by a PTM GetStatus() Request to an Endpoint <\/td>\n<\/tr>\n
388<\/td>\n9.4.7 Set Configuration
9.4.8 Set Descriptor <\/td>\n<\/tr>\n
389<\/td>\n9.4.9 Set Feature <\/td>\n<\/tr>\n
390<\/td>\n9.4.10 Set Interface
Table 9-9 \u2013 Suspend Options <\/td>\n<\/tr>\n
391<\/td>\n9.4.11 Set Isochronous Delay
9.4.12 Set SEL <\/td>\n<\/tr>\n
392<\/td>\n9.4.13 Synch Frame
9.4.14 Events and Their Effect on Device Parameters <\/td>\n<\/tr>\n
393<\/td>\n9.5 Descriptors
Table 9-10 \u2013 Device Parameters and Events <\/td>\n<\/tr>\n
394<\/td>\n9.6 Standard USB Descriptor Definitions
9.6.1 Device <\/td>\n<\/tr>\n
396<\/td>\nTable 9-11 \u2013 Standard Device Descriptor <\/td>\n<\/tr>\n
397<\/td>\n9.6.2 Binary Device Object Store (BOS)
Table 9-12 \u2013 BOS Descriptor
Table 9-13 \u2013 Format of a Device Capability Descriptor <\/td>\n<\/tr>\n
398<\/td>\nTable 9-14 \u2013 Device Capability Type Codes
Table 9-15 \u2013 USB 2.0 Extension Descriptor <\/td>\n<\/tr>\n
400<\/td>\nTable 9-16 \u2013 SuperSpeed Device Capability Descriptor <\/td>\n<\/tr>\n
401<\/td>\nTable 9-17 \u2013 Container ID Descriptor <\/td>\n<\/tr>\n
402<\/td>\nTable 9-18 \u2013 Platform Descriptor <\/td>\n<\/tr>\n
403<\/td>\nTable 9-19 \u2013 SuperSpeedPlus Descriptor <\/td>\n<\/tr>\n
405<\/td>\n9.6.3 Configuration
Table 9-20 \u2013 PTM Capability Descriptor <\/td>\n<\/tr>\n
406<\/td>\n9.6.4 Interface Association
Table 9-21 \u2013 Standard Configuration Descriptor <\/td>\n<\/tr>\n
407<\/td>\n9.6.5 Interface
Table 9-22 \u2013 Standard Interface Association Descriptor <\/td>\n<\/tr>\n
409<\/td>\n9.6.6 Endpoint
Table 9-23 \u2013 Standard Interface Descriptor <\/td>\n<\/tr>\n
410<\/td>\nTable 9-24 \u2013 Standard Endpoint Descriptor <\/td>\n<\/tr>\n
411<\/td>\nTable 9-25 \u2013 Example of Feedback Endpoint Numbers <\/td>\n<\/tr>\n
412<\/td>\n9.6.7 SuperSpeed Endpoint Companion
Figure 9-8 \u2013 Example of Feedback Endpoint Relationships <\/td>\n<\/tr>\n
413<\/td>\nTable 9-26 \u2013 SuperSpeed Endpoint Companion Descriptor <\/td>\n<\/tr>\n
414<\/td>\n9.6.8 SuperSpeedPlus Isochronous Endpoint Companion
Table 9-27 \u2013 SuperSpeedPlus Isochronous Endpoint Companion Descriptor <\/td>\n<\/tr>\n
415<\/td>\n9.6.9 String
9.7 Device Class Definitions
9.7.1 Descriptors
Table 9-28 \u2013 String Descriptor Zero, Specifying Languages Supported by the Device
Table 9-29 \u2013 UNICODE String Descriptor <\/td>\n<\/tr>\n
416<\/td>\n9.7.2 Interface(s)
9.7.3 Requests
10 Hub, Host Downstream Port, and Device Upstream Port Specification
10.1 Hub Feature Summary <\/td>\n<\/tr>\n
417<\/td>\nFigure 10-1 \u2013 USB Hub Architecture <\/td>\n<\/tr>\n
418<\/td>\nFigure 10-2 \u2013 SuperSpeed Portion of the USB Hub Architecture <\/td>\n<\/tr>\n
419<\/td>\nFigure 10-3 \u2013 SuperSpeedPlus Portion of the Hub Architecture <\/td>\n<\/tr>\n
420<\/td>\n10.1.1 Connecting to an Enhanced SuperSpeed Capable Host
10.1.2 Connecting to a USB 2.0 Host
Figure 10-4 \u2013 Simple USB Topology <\/td>\n<\/tr>\n
421<\/td>\n10.1.3 Hub Connectivity <\/td>\n<\/tr>\n
422<\/td>\nFigure 10-5 \u2013 Route String Example <\/td>\n<\/tr>\n
423<\/td>\n10.1.4 Resume Connectivity
Figure 10-6 \u2013 SuperSpeed Hub Signaling Connectivity <\/td>\n<\/tr>\n
424<\/td>\n10.1.5 Hub Fault Recovery Mechanisms
10.1.6 Hub Buffer Architecture
Figure 10-7 \u2013 Resume Connectivity <\/td>\n<\/tr>\n
425<\/td>\nFigure 10-8 \u2013 Typical SuperSpeed Hub Header Packet Buffer Architecture
Figure 10-9 \u2013 SuperSpeed Hub Data Buffer Traffic (Header Packet Buffer Only Shown for DS Port 1) <\/td>\n<\/tr>\n
426<\/td>\n10.2 Hub Power Management
10.2.1 Link States
10.2.2 Hub Downstream Port U1\/U2 Timers
10.2.3 Downstream\/Upstream Port Link State Transitions <\/td>\n<\/tr>\n
427<\/td>\n10.3 Hub Downstream Facing Ports <\/td>\n<\/tr>\n
428<\/td>\nFigure 10-10 \u2013 Downstream Facing Hub Port State Machine <\/td>\n<\/tr>\n
429<\/td>\nTable 10-1 \u2013 Downstream Facing Hub Port State Machine Diagram Legend <\/td>\n<\/tr>\n
430<\/td>\n10.3.1 Hub Downstream Facing Port State Descriptions <\/td>\n<\/tr>\n
431<\/td>\nTable 10-2 \u2013 Downstream Port Vbus Requirements <\/td>\n<\/tr>\n
434<\/td>\n10.3.2 Disconnect Detect Mechanism <\/td>\n<\/tr>\n
435<\/td>\n10.3.3 Labeling
10.4 Hub Downstream Facing Port Power Management
10.4.1 Downstream Facing Port PM Timers <\/td>\n<\/tr>\n
436<\/td>\n10.4.2 Hub Downstream Facing Port State Descriptions
Figure 10-11 \u2013 Downstream Facing Hub Port Power Management State Machine <\/td>\n<\/tr>\n
439<\/td>\n10.5 Hub Upstream Facing Port <\/td>\n<\/tr>\n
440<\/td>\n10.5.1 Upstream Facing Port State Descriptions
Figure 10-12 \u2013 Upstream Facing Hub Port State Machine <\/td>\n<\/tr>\n
442<\/td>\n10.5.2 Hub Connect State Machine
Figure 10-13 \u2013 Hub Connect (HCONNECT) State Machine <\/td>\n<\/tr>\n
443<\/td>\n10.6 Upstream Facing Port Power Management <\/td>\n<\/tr>\n
444<\/td>\n10.6.1 Upstream Facing Port PM Timer
Figure 10-14 \u2013 Upstream Facing Hub Port Power Management State Machine <\/td>\n<\/tr>\n
445<\/td>\n10.6.2 Hub Upstream Facing Port State Descriptions <\/td>\n<\/tr>\n
447<\/td>\n10.7 SuperSpeed Hub Header Packet Forwarding and Data Repeater <\/td>\n<\/tr>\n
448<\/td>\n10.7.1 SuperSpeed Hub Elasticity Buffer
10.7.2 SKP Ordered Sets
10.7.3 Interpacket Spacing
10.7.4 SuperSpeed Header Packet Buffer Architecture
Figure 10-15 \u2013 Example SS Hub Header Packet Buffer Architecture \u2013 Downstream Traffic <\/td>\n<\/tr>\n
449<\/td>\n10.7.5 SuperSpeed Packet Connectivity
Figure 10-16 \u2013 Example SS Hub Header Packet Buffer Architecture \u2013 Upstream Traffic <\/td>\n<\/tr>\n
450<\/td>\n10.8 SuperSpeedPlus Store and Forward Behavior
10.8.1 Hub Elasticity Buffer
10.8.2 SKP Ordered Sets
10.8.3 Interpacket Spacing
10.8.4 Upstream Flowing Buffering <\/td>\n<\/tr>\n
451<\/td>\n10.8.5 Downstream Flowing Buffering
Figure 10-17 \u2013 Logical Representation of Upstream Flowing Buffers
Figure 10-18 \u2013 Logical Representation of Downstream Flowing Buffers <\/td>\n<\/tr>\n
452<\/td>\n10.8.6 SuperSpeedPlus Hub Arbitration of Packets <\/td>\n<\/tr>\n
454<\/td>\n10.8.7 SuperSpeedPlus Upstream Flowing Packet Modifications <\/td>\n<\/tr>\n
455<\/td>\n10.8.8 SuperSpeedPlus Downstream Controller
10.9 Port State Machines
10.9.1 Port Transmit State Machine <\/td>\n<\/tr>\n
456<\/td>\n10.9.2 Port Transmit State Descriptions
Figure 10-19 \u2013 Port Transmit State Machine <\/td>\n<\/tr>\n
457<\/td>\n10.9.3 Port Receive State Machine <\/td>\n<\/tr>\n
458<\/td>\n10.9.4 Port Receive State Descriptions
Figure 10-20 \u2013 Upstream Facing Port Rx State Machine <\/td>\n<\/tr>\n
459<\/td>\nTable 10-3 \u2013 Downstream Flowing Header Packet Processing Actions <\/td>\n<\/tr>\n
463<\/td>\n10.10 Suspend and Resume
10.11 Hub Upstream Port Reset Behavior <\/td>\n<\/tr>\n
464<\/td>\n10.12 Hub Port Power Control
10.12.1 Multiple Gangs
10.13 Hub Controller <\/td>\n<\/tr>\n
465<\/td>\n10.13.1 Endpoint Organization
10.13.2 Hub Information Architecture and Operation
Figure 10-21 \u2013 Example Hub Controller Organization <\/td>\n<\/tr>\n
466<\/td>\n10.13.3 Port Change Information Processing
Figure 10-22 \u2013 Relationship of Status, Status Change, and Control Information to Device States <\/td>\n<\/tr>\n
467<\/td>\n10.13.4 Hub and Port Status Change Bitmap
Figure 10-23 \u2013 Port Status Handling Method <\/td>\n<\/tr>\n
468<\/td>\n10.13.5 Over-current Reporting and Recovery
Figure 10-24 \u2013 Hub and Port Status Change Bitmap
Figure 10-25 \u2013 Example Hub and Port Change Bit Sampling <\/td>\n<\/tr>\n
469<\/td>\n10.13.6 Enumeration Handling
10.14 Hub Configuration <\/td>\n<\/tr>\n
470<\/td>\n10.15 Descriptors
Table 10-4 \u2013 Hub Power Operating Mode Summary <\/td>\n<\/tr>\n
471<\/td>\n10.15.1 Standard Descriptors for Hub Class <\/td>\n<\/tr>\n
476<\/td>\n10.15.2 Class-specific Descriptors <\/td>\n<\/tr>\n
477<\/td>\nTable 10-5 \u2013 Enhanced SuperSpeed Hub Descriptor <\/td>\n<\/tr>\n
478<\/td>\n10.16 Requests
10.16.1 Standard Requests <\/td>\n<\/tr>\n
479<\/td>\n10.16.2 Class-specific Requests
Table 10-6 \u2013 Hub Responses to Standard Device Requests <\/td>\n<\/tr>\n
480<\/td>\nTable 10-7 \u2013 Hub Class Requests
Table 10-8 \u2013 Hub Class Request Codes <\/td>\n<\/tr>\n
481<\/td>\nTable 10-9 \u2013 Hub Class Feature Selectors <\/td>\n<\/tr>\n
483<\/td>\nTable 10-10 \u2013 Hub Status Field, wHubStatus <\/td>\n<\/tr>\n
484<\/td>\nTable 10-11 \u2013 Hub Change Field, wHubChange <\/td>\n<\/tr>\n
485<\/td>\nTable 10-12 \u2013 Port Status Type Codes <\/td>\n<\/tr>\n
486<\/td>\nTable 10-13 \u2013 Port Status Field, wPortStatus <\/td>\n<\/tr>\n
489<\/td>\nTable 10-14 \u2013 Port Change Field, wPortChange <\/td>\n<\/tr>\n
491<\/td>\nTable 10-15 \u2013 Extended Port Status Field, dwExtPortStatus <\/td>\n<\/tr>\n
493<\/td>\nTable 10-16 \u2013 U1 Timeout Value Encoding
Table 10-17 \u2013 U2 Timeout Value Encoding <\/td>\n<\/tr>\n
495<\/td>\nTable 10-18 \u2013 Downstream Port Remote Wake Mask Encoding <\/td>\n<\/tr>\n
496<\/td>\n10.17 Host Root (Downstream) Ports
10.18 Peripheral Device Upstream Ports
10.18.1 Peripheral Device Upstream Ports <\/td>\n<\/tr>\n
497<\/td>\n10.18.2 Peripheral Device Upstream Port State Machine
Figure 10-26 \u2013 Peripheral Upstream Device Port State Machine <\/td>\n<\/tr>\n
499<\/td>\n10.19 Hub Chapter Parameters <\/td>\n<\/tr>\n
500<\/td>\nTable 10-19 \u2013 Hub Parameters <\/td>\n<\/tr>\n
501<\/td>\n11 Interoperability and Power Delivery <\/td>\n<\/tr>\n
502<\/td>\n11.1 USB 3.1 Host Support for USB 2.0
11.2 USB 3.1 Hub Support for USB 2.0
Table 11-1 \u2013 USB 3.0 and USB 2.0 Interoperability <\/td>\n<\/tr>\n
503<\/td>\n11.3 USB 3.1 Device Support for USB 2.0
11.4 Power Distribution
11.4.1 Classes of Devices and Connections <\/td>\n<\/tr>\n
504<\/td>\nFigure 11-1 \u2013 Compound Self-powered Hub <\/td>\n<\/tr>\n
505<\/td>\nFigure 11-2 \u2013 Low-power Bus-powered Function
Figure 11-3 \u2013 High-power Bus-powered Function <\/td>\n<\/tr>\n
506<\/td>\n11.4.2 Steady-State Voltage Drop Budget
Figure 11-4 \u2013 Self-powered Function
Figure 11-5 \u2013 Worst-case Voltage Drop Topology (Steady State) <\/td>\n<\/tr>\n
507<\/td>\n11.4.3 Power Control During Suspend\/Resume
Figure 11-6 \u2013 Worst-case Voltage Drop Analysis Using Equivalent Resistance <\/td>\n<\/tr>\n
508<\/td>\n11.4.4 Dynamic Attach and Detach
Figure 11-7 \u2013 Typical Suspend Current Averaging Profile <\/td>\n<\/tr>\n
509<\/td>\n11.4.5 Vbus Electrical Characteristics
11.4.6 Powered-B Connector
11.4.7 Wire Gauge Table
Table 11-2 \u2013 DC Electrical Characteristics <\/td>\n<\/tr>\n
510<\/td>\nTable 11-3 \u2013 Vbus\/Gnd Wire Gauge vs. Maximum Length <\/td>\n<\/tr>\n
511<\/td>\nTable A.1 \u2013 8b\/10b Data Symbol Codes <\/td>\n<\/tr>\n
517<\/td>\nTable A.2 \u2013 8b\/10b Special Character Symbol Codes <\/td>\n<\/tr>\n
525<\/td>\nTable C.1 \u2013 Link States and Characteristics Summary <\/td>\n<\/tr>\n
534<\/td>\nFigure C.1 \u2013 Flow Diagram for Host Initiated Wakeup <\/td>\n<\/tr>\n
535<\/td>\nFigure C.2 \u2013 Device Total Intrinsic Latency Tolerance <\/td>\n<\/tr>\n
537<\/td>\nFigure C.3 \u2013 Host to Device Path Exit Latency Calculation Examples <\/td>\n<\/tr>\n
538<\/td>\nFigure C.4 \u2013 Device Connected Directly to a Host <\/td>\n<\/tr>\n
539<\/td>\nFigure C.5 \u2013 Device Connected Through a Hub <\/td>\n<\/tr>\n
540<\/td>\nFigure C.6 \u2013 Downstream Host to Device Path Exit Latency with Hub <\/td>\n<\/tr>\n
541<\/td>\nFigure C.7 \u2013 Upstream Device to Host Path Exit Latency with Hub <\/td>\n<\/tr>\n
544<\/td>\nFigure C.8 \u2013 LT State Diagram <\/td>\n<\/tr>\n
547<\/td>\nFigure C.9 \u2013 System Power during SuperSpeed and High Speed Device Data Transfers <\/td>\n<\/tr>\n
548<\/td>\nFigure D.1 \u2013 Sample ERDY Transaction Packet
Figure D.2 \u2013 Sample Data Packet
Figure D.3 \u2013 Example placement of Gen 2 SKP Block, Idle Symbols, Link Command and Header Packet <\/td>\n<\/tr>\n
549<\/td>\nFigure D.4 \u2013 Example placement of Gen 2 Data Packets and Idle Symbols <\/td>\n<\/tr>\n
550<\/td>\nFigure E.1 \u2013 Link segment definition <\/td>\n<\/tr>\n
551<\/td>\nFigure E.2 \u2013 Retimer implementation examples <\/td>\n<\/tr>\n
552<\/td>\nFigure E.3 \u2013 Example high level retimer architecture in Gen 2 operation <\/td>\n<\/tr>\n
555<\/td>\nFigure E.4 \u2013 Retimer Training and Status State Machine <\/td>\n<\/tr>\n
557<\/td>\nFigure E.5 \u2013 Polling Substate Machine <\/td>\n<\/tr>\n
565<\/td>\nFigure E.6 \u2013 Recovery Substate Machine <\/td>\n<\/tr>\n
568<\/td>\nFigure E.7 \u2013 Example block diagram of a retimer operating at SuperSpeed <\/td>\n<\/tr>\n
571<\/td>\nTable 6-13 \u2013 Compliance Pattern Sequences <\/td>\n<\/tr>\n
572<\/td>\nTable 6-13 \u2013 Compliance Pattern Sequences <\/td>\n<\/tr>\n
573<\/td>\nTable 6-17 \u2013 Transmitter Normative Electrical Parameters <\/td>\n<\/tr>\n
574<\/td>\nTable 6-17 \u2013 Transmitter Normative Electrical Parameters <\/td>\n<\/tr>\n
575<\/td>\nFigure 6-20 \u2013 De-Emphasis Waveform <\/td>\n<\/tr>\n
576<\/td>\nFigure 6-21 \u2013 3-tap Transmit Equalizer Structure
Figure 6-22 \u2013 Example Output Waveform for 3-tap Transmit Equalizer <\/td>\n<\/tr>\n
577<\/td>\nTable 6-20 \u2013 Informative Gen 2 Transmitter Equalization Settings <\/td>\n<\/tr>\n
578<\/td>\nFigure 6-20 \u2013 De-Emphasis Waveform <\/td>\n<\/tr>\n
579<\/td>\nFigure 6-21 \u2013 3-tap Transmit Equalizer Structure
Figure 6-22 \u2013 Example Output Waveform for 3-tap Transmit Equalizer <\/td>\n<\/tr>\n
580<\/td>\nTable 6-20 \u2013 Informative Gen 2 Transmitter Equalization Settings <\/td>\n<\/tr>\n
581<\/td>\nFigure 6-23 \u2013 Example waveforms for measuring transmitter equalization <\/td>\n<\/tr>\n
582<\/td>\nFigure 6-25 \u2013 Gen 2 Compliance Rx EQ Transfer Function <\/td>\n<\/tr>\n
583<\/td>\nFigure 6-25 \u2013 Gen 2 Compliance Rx EQ Transfer Function <\/td>\n<\/tr>\n
584<\/td>\nTable 6-27 \u2013 Input Jitter Requirements for Rx Tolerance Testing <\/td>\n<\/tr>\n
585<\/td>\nTable 6-27 \u2013 Input Jitter Requirements for Rx Tolerance Testing <\/td>\n<\/tr>\n
590<\/td>\nTable 11-4 \u2013 Link Command Bit Definitions <\/td>\n<\/tr>\n
591<\/td>\nTable 11-5 \u2013 Link Command Bit Definitions <\/td>\n<\/tr>\n
613<\/td>\nTable 11-6 \u2013 Gen 2 SKP Ordered Set <\/td>\n<\/tr>\n
614<\/td>\nTable 11-7 \u2013 Gen 2 SKP Ordered Set <\/td>\n<\/tr>\n
619<\/td>\nTable 11-8 \u2013 SDS Ordered Set <\/td>\n<\/tr>\n
620<\/td>\nTable 11-9 \u2013 SDS Ordered Set <\/td>\n<\/tr>\n
622<\/td>\nTable 6-29 \u2013 LFPS Transmitter Timing for SuperSpeed Designs1
Table 6-29 \u2013 LFPS Transmitter Timing for SuperSpeed Designs1 <\/td>\n<\/tr>\n
624<\/td>\nTable 6-15 \u2013 Informative Jitter Budgeting at the Silicon Pads
Table 6-15 \u2013 Informative Jitter Budgeting at the Silicon Pads <\/td>\n<\/tr>\n
625<\/td>\nTable 6-19 \u2013 Normative Transmitter Eye Mask at Test Point TP1
Table 6-19 \u2013 Normative Transmitter Eye Mask at Test Point TP1 <\/td>\n<\/tr>\n
626<\/td>\nTable 6-27 \u2013 Input Jitter Requirements for Rx Tolerance Testing <\/td>\n<\/tr>\n
627<\/td>\nTable 6-27 \u2013 Input Jitter Requirements for Rx Tolerance Testing <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Universal Serial Bus interfaces for data and power – Universal Serial Bus 3.1 Specification (IEC 62680-3-1:2017)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2017<\/td>\n644<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":229152,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2641],"product_tag":[],"class_list":{"0":"post-229147","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-bsi","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/229147","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/229152"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=229147"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=229147"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=229147"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}