This part of IEC 60749 establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD).<\/p>\n
The purpose of this document is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels.<\/p>\n
ESD testing of semiconductor devices is selected from this test method, the machine model (MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series. Unless otherwise specified, this test method is the one selected.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 5<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 4 Apparatus and required equipment 4.1 Waveform verification equipment <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 4.2 Oscilloscope 4.3 Additional requirements for digital oscilloscopes 4.4 Current transducer (inductive current probe) 4.5 Evaluation loads <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 4.6 Human body model simulator 4.7 HBM test equipment parasitic properties 5 Stress test equipment qualification and routine verification 5.1 Overview of required HBM tester evaluations Figures Figure 1 \u2013 Simplified HBM simulator circuit with loads <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 5.2 Measurement procedures 5.2.1 Reference pin pair determination 5.2.2 Waveform capture with current probe <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 5.2.3 Determination of waveform parameters <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Figure 2 \u2013 Current waveform through shorting wires <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | Figure 3 \u2013 Current waveform through a 500 \u2126 resistor <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 5.2.4 High voltage discharge path test 5.3 HBM tester qualification 5.3.1 HBM ESD tester qualification requirements 5.3.2 HBM tester qualification procedure Figure 4 \u2013 Peak current short circuit ringing waveform <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 5.4 Test fixture board qualification for socketed testers <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 5.5 Routine waveform check requirements 5.5.1 Standard routine waveform check description 5.5.2 Waveform check frequency Tables Table 1 \u2013 Waveform specification <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | 5.5.3 Alternate routine waveform capture procedure 5.6 High voltage discharge path check 5.6.1 Relay testers 5.6.2 Non-relay testers 5.7 Tester waveform records 5.7.1 Tester and test fixture board qualification records 5.7.2 Periodic waveform check records <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | 5.8 Safety 5.8.1 Initial set-up 5.8.2 Training 5.8.3 Personnel safety 6 Classification procedure 6.1 Devices for classification 6.2 Parametric and functional testing 6.3 Device stressing <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | 6.4 Pin categorization 6.4.1 General 6.4.2 No connect pins <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 6.4.3 Supply pins 6.4.4 Non-supply pins <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | 6.5 Pin groupings 6.5.1 Supply pin groups 6.5.2 Shorted non-supply pin groups 6.6 Pin stress combinations 6.6.1 Pin stress combination categorization <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Table 2 \u2013 Preferred pin combinations sets <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | 6.6.2 Non-supply and supply to supply combinations (1, 2, \u2026 N) Table 3 \u2013 Alternative pin combinations sets <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | 6.6.3 Non-supply to non-supply combinations <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | 6.7 HBM stressing with a low-parasitic simulator 6.7.1 Low-parasitic HBM simulator 6.7.2 Requirements for low parasitics 6.8 Testing after stressing 7 Failure criteria 8 Component classification <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | Table 4 \u2013 HBM ESD component classification levels <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Annex A (informative)HBM test method flow chart Figure A.1 \u2013 HBM test method flow chart (1 of 3) <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | Annex B (informative)HBM test equipment parasitic properties B.1 Optional trailing pulse detection equipment \/ apparatus Figure B.1 \u2013 Diagram of trailing pulse measurement setup <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | B.2 Optional pre-pulse voltage rise test equipment Figure B.2 \u2013 Positive stress at 4 000 V Figure B.3 \u2013 Negative stress at 4 000 V <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Figure B.4 \u2013 Illustration of measuring voltage before HBM pulsewith a Zener diode or a device Figure B.5 \u2013 Example of voltage rise before the HBM current pulseacross a 9,4 V Zener diode <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | B.3 Open-relay tester capacitance parasitics B.4 Test to determine if an HBM simulator is a low-parasitic simulator <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | Figure B.6 \u2013 Diagram of a 10-pin shorting test device showing current probe <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | Annex C (informative)Example of testing a product using Table 2, Table 3,or Table 2 with a two-pin HBM tester C.1 General Figure C.1 \u2013 Example to demonstrate the idea of the partitioned test <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | C.2 Procedure A (following Table 2): <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | C.3 Alternative procedure B (following Table 3): Table C.1 \u2013 Product testing in accordance with Table 2 <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | C.4 Alternative procedure C (following Table 2): Table C.2 \u2013 Product testing in accordance with Table 3 <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | Table C.3 \u2013 Alternative product testing in accordance with Table 2 <\/td>\n<\/tr>\n | ||||||
| 46<\/td>\n | Annex D (informative)Examples of coupled non-supply pin pairs <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | Annex E (normative)Cloned non-supply (I\/O) pin sampling test method E.1 Purpose and overview E.2 Pin sampling overview and statistical details <\/td>\n<\/tr>\n | ||||||
| 48<\/td>\n | E.3 IC product selections Figure E.1 \u2013 SPL, V1, VM, and z with the Bell shapedistribution pin failure curve <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | E.4 Randomly selecting and testing cloned I\/O pins E.5 Determining if sampling can be used with the supplied Excel spreadsheet E.5.1 Using the supplied Excel spreadsheet E.5.2 Without using the Excel spreadsheet E.6 HBM testing with a sample of cloned I\/O pins <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | E.7 Examples of testing with sampled cloned I\/Os <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | Figure E.2 \u2013 I\/O sampling test method flow chart <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Mechanical and climatic test methods – Electrostatic discharge (ESD) sensitivity testing. Human body model (HBM)<\/b><\/p>\n |