{"id":80113,"date":"2024-10-17T18:41:03","date_gmt":"2024-10-17T18:41:03","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1394a-2000\/"},"modified":"2024-10-24T19:42:29","modified_gmt":"2024-10-24T19:42:29","slug":"ieee-1394a-2000","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1394a-2000\/","title":{"rendered":"IEEE 1394a 2000"},"content":{"rendered":"

– Inactive – Superseded. Amended information for a high-speed Serial Bus that integrates well with most IEEE stan-dard 32-bit and 64-bit parallel buses is specified. This amendment is intended to extend the usefulness of a low-cost interconnect between external peripherals, as described in IEEE Std 1394-1995. This amendment to IEEE Std 1394-1995 follows the ISO\/IEC 13213:1994 Command and Status Register (CSR) Architecture.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle Page <\/td>\n<\/tr>\n
3<\/td>\nIntroduction <\/td>\n<\/tr>\n
4<\/td>\nPatent Notice
Participants <\/td>\n<\/tr>\n
7<\/td>\nCONTENTS <\/td>\n<\/tr>\n
9<\/td>\n0. Introduction
0.1 Scope <\/td>\n<\/tr>\n
10<\/td>\n0.2 Purpose
0.3 Document organization <\/td>\n<\/tr>\n
11<\/td>\n1. Overview
1.2 References <\/td>\n<\/tr>\n
12<\/td>\n1.5 Service model <\/td>\n<\/tr>\n
13<\/td>\n1.6 Document notation
1.6.1 Mechanical notation
1.6.2 Signal naming
1.6.3 Size notation <\/td>\n<\/tr>\n
14<\/td>\n1.6.4 Numerical values
1.6.5 Packet formats <\/td>\n<\/tr>\n
15<\/td>\n1.6.6 Register formats
1.6.7 C code notation <\/td>\n<\/tr>\n
16<\/td>\n1.6.8 State machine notation
1.6.9 CSR, ROM, and field notation <\/td>\n<\/tr>\n
17<\/td>\n1.6.10 Register specification format <\/td>\n<\/tr>\n
18<\/td>\n1.6.11 Reserved CSR fields <\/td>\n<\/tr>\n
19<\/td>\n2. Definitions and abbreviations
2.1 Conformance
2.2 Technical glossary <\/td>\n<\/tr>\n
23<\/td>\n3. Summary description
3.9 New features of IEEE Std 1394a-2000
3.9.1 Connection debounce <\/td>\n<\/tr>\n
24<\/td>\n3.9.2 Cable arbitration enhancements
3.9.2.1 Arbitrated (short) bus reset <\/td>\n<\/tr>\n
25<\/td>\n3.9.2.2 Ack-accelerated arbitration <\/td>\n<\/tr>\n
26<\/td>\n3.9.2.3 Fly-by concatenation
3.9.2.4 Multi-speed-packet concatenation <\/td>\n<\/tr>\n
27<\/td>\n3.9.2.5 Arbitration enhancements and cycle start
3.9.3 Performance optimization via PHY \u201cpinging\u201d\u009d <\/td>\n<\/tr>\n
28<\/td>\n3.9.4 Priority arbitration
3.9.5 Port disable, suspend, and resume <\/td>\n<\/tr>\n
29<\/td>\n3.9.5.1 Connection detect circuit
3.9.5.2 Suspended connection <\/td>\n<\/tr>\n
30<\/td>\n3.9.5.3 Suspended domain
3.9.5.4 Resumption <\/td>\n<\/tr>\n
31<\/td>\n3.9.5.5 Boundary nodes <\/td>\n<\/tr>\n
32<\/td>\n4. Cable PHY specification
4.2 Cable physical connection specification
4.2.1 Media attachment
4.2.1.4 Signal propagation performance
4.2.1.4.8 Shield ac coupling <\/td>\n<\/tr>\n
33<\/td>\n4.2.1A Alternative cable media attachment specification
4.2.1A.1 Connectors
4.2.1A.1.1 Connector plug <\/td>\n<\/tr>\n
34<\/td>\n4.2.1A.1.2 Connector plug terminations
4.2.1A.1.3 Connector socket <\/td>\n<\/tr>\n
37<\/td>\n4.2.1A.1.4 Contact finish on plug and socket contacts
4.2.1A.1.5 Termination finish on plug and contact socket terminals
4.2.1A.1.6 Shell finish on plugs and sockets
4.2.1A.1.7 Connector durability <\/td>\n<\/tr>\n
38<\/td>\n4.2.1A.1.8 Printed circuit board footprints
4.2.1A.2 Cables
4.2.1A.2.1 Cable material (informative) <\/td>\n<\/tr>\n
39<\/td>\n4.2.1A.2.2 Cable assemblies <\/td>\n<\/tr>\n
40<\/td>\n4.2.1A.3 Connector and cable assembly performance criteria <\/td>\n<\/tr>\n
41<\/td>\n4.2.1A.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functiona… <\/td>\n<\/tr>\n
42<\/td>\n4.2.1A.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and … <\/td>\n<\/tr>\n
43<\/td>\n4.2.1A.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity … <\/td>\n<\/tr>\n
44<\/td>\n4.2.1A.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling … <\/td>\n<\/tr>\n
45<\/td>\n4.2.1A.3.5 Performance group E: Contact resistance and unmating force when subjected to temperatu… <\/td>\n<\/tr>\n
47<\/td>\n4.2.1A.3.6 Performance group F: Mechanical retention and durability
4.2.1A.3.7 Performance group G: General tests <\/td>\n<\/tr>\n
49<\/td>\n4.2.1A.4 Signal propagation performance criteria
4.2.1A.4.1 Signal impedance
4.2.1A.4.2 Signal pairs attenuation
4.2.1A.4.3 Signal pairs propagation delay <\/td>\n<\/tr>\n
50<\/td>\n4.2.1A.4.4 Signal pairs relative propagation skew
4.2.1A.4.5 Crosstalk
4.2.2 Media signal interface <\/td>\n<\/tr>\n
51<\/td>\n4.2.2 Media signal interface
4.2.2 Port interface <\/td>\n<\/tr>\n
53<\/td>\n4.2.2.7 Cable power and ground <\/td>\n<\/tr>\n
55<\/td>\n4.2.3 Media signal timing
4.2.3.2 Data signal rise and fall times <\/td>\n<\/tr>\n
56<\/td>\n4.3 Cable PHY facilities
4.3.3 Cable PHY line states
4.3.4 Cable PHY packets <\/td>\n<\/tr>\n
57<\/td>\n4.3.4.1 Self-ID packets <\/td>\n<\/tr>\n
59<\/td>\n4.3.4.2 Link-on packet
4.3.4.3 PHY configuration packet <\/td>\n<\/tr>\n
60<\/td>\n4.3.4.4 Extended PHY packets
4.3.4.4.1 Ping packet <\/td>\n<\/tr>\n
61<\/td>\n4.3.4.4.2 Remote access packet
4.3.4.4.3 Remote reply packet <\/td>\n<\/tr>\n
62<\/td>\n4.3.4.4.4 Remote command packet <\/td>\n<\/tr>\n
63<\/td>\n4.3.4.4.5 Remote confirmation packet
4.3.4.4.6 Resume packet <\/td>\n<\/tr>\n
64<\/td>\n4.3.5 Cable PHY timing constants
4.3.5 Cable interface timing constants <\/td>\n<\/tr>\n
68<\/td>\n4.3.6 Gap timing <\/td>\n<\/tr>\n
69<\/td>\n4.3.8 Node variables <\/td>\n<\/tr>\n
70<\/td>\n4.3.9 Port variables
4.4 Cable physical layer operation <\/td>\n<\/tr>\n
74<\/td>\n4.4.1 Speed-signal sampling and filtering <\/td>\n<\/tr>\n
76<\/td>\n4.4.2 Data transmission and reception
4.4.2.1 Data transmission <\/td>\n<\/tr>\n
77<\/td>\n4.4.2.2 Data reception and repeat <\/td>\n<\/tr>\n
80<\/td>\n4.4.3 Arbitration
4.4.3.1 Bus reset
4.4.3.1.1 Bus reset state machine notes <\/td>\n<\/tr>\n
81<\/td>\n4.4.3.1.2 Bus reset actions and conditions <\/td>\n<\/tr>\n
83<\/td>\n4.4.3.2 Tree identify
4.4.3.2.1 Tree ID state machine notes <\/td>\n<\/tr>\n
85<\/td>\n4.4.3.2.2 Tree ID actions and conditions <\/td>\n<\/tr>\n
86<\/td>\n4.4.3.3 Self-identify
4.4.3.3.1 Self-ID state machine notes <\/td>\n<\/tr>\n
88<\/td>\n4.4.3.3.2 Self-ID actions and conditions <\/td>\n<\/tr>\n
90<\/td>\n4.4.3.4 Normal arbitration
4.4.3.4.1 Normal arbitration state machine notes <\/td>\n<\/tr>\n
93<\/td>\n4.4.3.4.2 Normal arbitration actions and conditions <\/td>\n<\/tr>\n
95<\/td>\n4.4.3.4.3 Receive actions and conditions <\/td>\n<\/tr>\n
96<\/td>\n4.4.3.4.4 Transmit actions and conditions <\/td>\n<\/tr>\n
97<\/td>\n4.4.3.4.5 PHY response actions and conditions <\/td>\n<\/tr>\n
99<\/td>\n4.4.4 Port connection
4.4.4.1 Port connection state machine notes <\/td>\n<\/tr>\n
102<\/td>\n4.4.4.2 Port connection actions and conditions <\/td>\n<\/tr>\n
106<\/td>\n5A. PHY\/link interface specification <\/td>\n<\/tr>\n
133<\/td>\n5B. PHY register map <\/td>\n<\/tr>\n
141<\/td>\n6. Link layer specification
6.1 Link layer services
6.1.1 Link layer bus management services for the node controller
6.1.1.3 Link event indication (LK_EVENT.indication)
6.1.2 Link layer asynchronous data services for the transaction layer
6.1.2.3 Link data indication (LK_DATA.indication) <\/td>\n<\/tr>\n
142<\/td>\n6.1.3 Link layer isochronous data services for application layers
6.1.3.4 Link isochronous indication (LK_ISO.indication)
6.2 Link layer facilities
6.2.2 Asynchronous packets
6.2.2.2 Asynchronous packet formats with data block payload
6.2.2.2.3 Cycle start <\/td>\n<\/tr>\n
143<\/td>\n6.2.2.3 Asynchronous packet formats with data block payload
6.2.2.3.3 Read response for data block
6.2.3 Isochronous packets
6.2.3.1 Isochronous data block packet format <\/td>\n<\/tr>\n
144<\/td>\n6.2.3A Asynchronous stream packets <\/td>\n<\/tr>\n
145<\/td>\n6.2.3A Asynchronous stream packets
6.2.3A.1 Asynchronous stream packet format
6.2.3A.2 Global asynchronous stream packet (GASP) format <\/td>\n<\/tr>\n
146<\/td>\n6.2.3A.3 Loose vs. strict isochronous packet reception <\/td>\n<\/tr>\n
147<\/td>\n6.2.4 Primary packet components
6.2.4.4 Retry code (rt)
6.2.4.5 Transaction codes (tcode) <\/td>\n<\/tr>\n
148<\/td>\n6.2.4.12 Tag
6.2.4.12 Tag (isochronous stream packets)
6.2.5 Acknowledge packets
6.2.5.2 ACK packet components
6.2.5.2.2 Acknowledge codes (ack_code) <\/td>\n<\/tr>\n
150<\/td>\n6.3 Link layer operation
6.3.1 Overview of link layer operation
6.3.1.1A Priority arbitration for PHY packets and response packets <\/td>\n<\/tr>\n
151<\/td>\n7. Transaction layer specification
7.1 Transaction layer services
7.1.2 Transaction layer data services for applications and bus management
7.1.2.1 Transaction data request (TRAN_DATA.request)
7.1.2.4 Transaction data response (TRAN_DATA.response) <\/td>\n<\/tr>\n
152<\/td>\n7.3 Transaction operation
7.3.1 Overview of transaction layer operations
7.3.1.3A Response codes (rcode)
7.3.1.3A.1 No response
7.3.1.3A.2 resp_complete
7.3.1.3A.3 resp_conflict_error <\/td>\n<\/tr>\n
153<\/td>\n7.3.1.3A.4 resp_data_error
7.3.1.3A.5 resp_type_error
7.3.1.3A.6 resp_address_error <\/td>\n<\/tr>\n
154<\/td>\n7.3.3 Details of transaction layer operation
7.3.3.1 Outbound transaction state machine
7.3.3.1.2 Sending a transaction request
7.3.3.1.3 Sending a transaction response
7.3.4 Transaction types
7.3.4.3 Lock transactions <\/td>\n<\/tr>\n
155<\/td>\n7.3.5 Retry protocols <\/td>\n<\/tr>\n
156<\/td>\n7.3.5.1 Outbound subaction retry protocol <\/td>\n<\/tr>\n
157<\/td>\n7.3.5.2 Inbound subaction single-phase retry protocol
7.3.5.3 Inbound subaction dual-phase retry protocol <\/td>\n<\/tr>\n
161<\/td>\n7.4 CSR Architecture transactions mapped to Serial Bus <\/td>\n<\/tr>\n
162<\/td>\n8. Serial Bus management specification
8.2 Serial Bus management services
8.2.1 Serial Bus control request (SB_CONTROL.request)
8.2.3 Serial Bus event indication (SB_EVENT.indication)
8.3 Serial Bus management facilities
8.3.1 Node capabilities taxonomy <\/td>\n<\/tr>\n
163<\/td>\n8.3.1.1 Repeater (cable environment)
8.3.1.2 Transaction capable
8.3.1.3 Isochronous capable
8.3.1.4 Cycle master capable <\/td>\n<\/tr>\n
164<\/td>\n8.3.1.5 Isochronous resource manager capable
8.3.1.6 Bus manager capable (cable environment) <\/td>\n<\/tr>\n
165<\/td>\n8.3.2 Command and status registers
8.3.2.2 CSR Architecture core registers
8.3.2.2.1 STATE_CLEAR register <\/td>\n<\/tr>\n
166<\/td>\n8.3.2.2.3 NODE_IDS register <\/td>\n<\/tr>\n
167<\/td>\n8.3.2.2.4 Command reset effects
8.3.2.2.6 SPLIT_TIMEOUT register <\/td>\n<\/tr>\n
168<\/td>\n8.3.2.3 Serial-Bus-dependent registers <\/td>\n<\/tr>\n
169<\/td>\n8.3.2.3.5A PRIORITY_BUDGET register <\/td>\n<\/tr>\n
170<\/td>\n8.3.2.3.7 BANDWIDTH_AVAILABLE register <\/td>\n<\/tr>\n
171<\/td>\n8.3.2.3.8 CHANNELS_AVAILABLE register <\/td>\n<\/tr>\n
172<\/td>\n8.3.2.3.11 BROADCAST_CHANNEL register <\/td>\n<\/tr>\n
173<\/td>\n8.3.2.4 Unit registers <\/td>\n<\/tr>\n
174<\/td>\n8.3.2.4.2 SPEED_MAP registers (cable environment)
8.3.2.5 Configuration ROM
8.3.2.5.4 Configuration ROM Bus_Info_Block <\/td>\n<\/tr>\n
177<\/td>\n8.4 Serial Bus management operations
8.4.2 Bus configuration procedures (cable environment)
8.4.2.3 Determination of the isochronous resource manager (cable environment) <\/td>\n<\/tr>\n
178<\/td>\n8.4.2.5 Determination of the bus manager (cable environment)
8.4.2.6 Determination of the cycle master (cable environment)
8.4.2.6A Determination of the root (cable environment) <\/td>\n<\/tr>\n
179<\/td>\n8.4.3 Isochronous management (cable environment)
8.4.3 Isochronous resource allocation (cable environment)
8.4.3.1 Bandwidth allocation <\/td>\n<\/tr>\n
180<\/td>\n8.4.3.2 Channel allocation <\/td>\n<\/tr>\n
181<\/td>\n8.4.5 Speed management (cable environment)
8.4.6 Topology management (cable environment)
8.4.6.2 Gap count optimization <\/td>\n<\/tr>\n
182<\/td>\n8.5 Bus configuration state machines (cable environment)
8.5.4 Abdication by the bus manager <\/td>\n<\/tr>\n
184<\/td>\nAnnex A\u2014Cable environment system properties <\/td>\n<\/tr>\n
188<\/td>\nAnnex C\u2014Internal device physical interface <\/td>\n<\/tr>\n
189<\/td>\nAnnex C1\u2014Transaction integrity safeguards <\/td>\n<\/tr>\n
190<\/td>\nAnnex E\u2014Cable operation and implementation examples <\/td>\n<\/tr>\n
194<\/td>\nAnnex K\u2014Serial Bus cable test procedures <\/td>\n<\/tr>\n
201<\/td>\nAnnex M\u2014Serial Bus topology considerations for power distribution (cable environment) <\/td>\n<\/tr>\n
204<\/td>\nAnnex N\u2014Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for a High Performance Serial Bus (Amendment)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2000<\/td>\n204<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80114,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-80113","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/80113","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80114"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=80113"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=80113"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=80113"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}