This part of IEC 62433 specifies macro-models for ICs to simulate conducted electromagnetic emissions on a printed circuit board. The model is commonly called Integrated Circuit Emission Model – Conducted Emission (ICEM-CE).<\/p>\n
The ICEM-CE model can also be used for modelling an IC-die, a functional block and an Intellectual Property block (IP).<\/p>\n
The ICEM-CE model can be used to model both digital and analogue ICs.<\/p>\n
Basically, conducted emissions have two origins:<\/p>\n
conducted emissions through power supply terminals and ground reference structures;<\/p>\n<\/li>\n
conducted emissions through input\/output (I\/O) terminals.<\/p>\n<\/li>\n<\/ul>\n
The ICEM-CE model addresses those two types of origins in a single approach.<\/p>\n
This standard defines structures and components of the macro-model for EMI simulation taking into account the IC\u2019s internal activities.<\/p>\n
This standard gives general data, which can be implemented in different formats or languages such as IBIS, IMIC, SPICE, VHDL-AMS and Verilog. SPICE is however chosen as default simulation environment to cover all the conducted emissions.<\/p>\n
This standard also specifies requirements for information that shall be incorporated in each ICEM-CE model or component part of the model for model circulation, but description syntax is not within the scope of this standard.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 6<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 4 Philosophy 4.1 General 4.2 Conducted emission from core activity (digital culprit) Figures Figure 1 \u2013 Decomposition example of a digital IC for conducted emissions analysis <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4.3 Conducted emission from I\/O activity 5 Basic components 5.1 General 5.2 Internal Activity (IA) Figure 2 \u2013 IA component <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 5.3 Passive Distribution Network (PDN) Figure 3 \u2013 Example of IA characteristics in the time domain Figure 4 \u2013 Example of IA characteristics in the frequency domain <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | Figure 5 \u2013 Example of a four-terminal PDN using lumped elements Figure 6 \u2013 Example of a seven-terminal PDN using distributed elements <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 6 IC macro-models 6.1 General 6.2 General IC macro-model Figure 7 \u2013 Example of a twelve-terminal PDN using matrix representation <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 6.3 Block-based IC macro-model Figure 8 \u2013 General IC macro-model Figure 9 \u2013 Example of block component <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | Figure 10 \u2013 Example of block components for I\/Os <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Figure 11 \u2013 Example of IBC with two internal terminals Figure 12 \u2013 Relationship between blocks and IBC <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Figure 13 \u2013 Block-based IC macro-model <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 6.4 Sub-model-based IC macro-model Figure 14 \u2013 Example of block-based IC macro-model <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | Figure 15 \u2013 Example of simple sub-model Figure 16 \u2013 Sub-model-based IC macro-model <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 7 Requirements for parameter extraction 7.1 General 7.2 Environmental extraction constraints 7.3 IA parameter extraction 7.4 PDN parameter extraction 7.5 IBC parameter extraction <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | Annex A (informative) Model parameter generation Table A.1 \u2013 Typical parameters for CMOS logic technologies <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Table A.2 \u2013 Typical number of logic gates vs. CPU technology Table A.3 \u2013 R, L and C parameters for various package types <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Figure A.1 \u2013 Typical characterization current gate schematic Figure A.2 \u2013 Current peak during switching transition <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | Figure A.3 \u2013 Example of IA extraction procedure from design Figure A.4 \u2013 Technology Influence <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | Figure A.5 \u2013 Final current waveform for a program period Figure A.6 \u2013 Comparison between measurement and simulation <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | Figure A.7 \u2013 Lumped element model of a package <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Figure A.8 \u2013 Circuit structure of the netlist <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | Figure A.9 \u2013 Principle of the IA computation Figure A.10 \u2013 Process involved to model iA(t) <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | Figure A.11 \u2013 iExt(t) measured using IEC 61967-4 Figure A.12 \u2013 iA(t)and iExt(t) profiles <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | Figure A.13 \u2013 Example of a hardware set-up used to extract the PDN parameters Figure A.14 \u2013 Miniature 50 \u2126 coaxial connectors <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Figure A.15 \u2013 Impedance probe using two miniature coaxial connectors Figure A.16 \u2013 Open and short terminations Figure A.17 \u2013 Measurement probe model <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | Figure A.18 \u2013 De-embedding principle <\/td>\n<\/tr>\n | ||||||
| 35<\/td>\n | Figure A.19 \u2013 Example of a predefined PDN structure Table A.4 \u2013 Measurement configurations and extracted RLC parameters <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | Figure A.20 \u2013 RL configuration Figure A.21 \u2013 RLC configuration <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | Figure A.22 \u2013 RLC with magnetic coupling configuration Figure A.23 \u2013 Impedance seen from Vcc and Gnd <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Figure A.24 \u2013 Complete PDN component <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | Figure A.25 \u2013 Set-up for correlation (left), measurement and prediction (right) Figure A.26 \u2013 Set-up used to measure the internal decoupling capacitor <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | Annex B (informative) Decoupling capacitors optimization Figure B.1 \u2013 Equivalent schematic of the complete electronic system <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | Figure B.2 \u2013 Impedance prediction and measurements <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | Annex C (informative) Conducted emission prediction Figure C.1 \u2013 IEC\u00a061967-4 test set-up standard Figure C.2 \u2013 Comparison between prediction and measurement <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | Annex D (informative) Conducted emission prediction at PCB level Figure D.1 \u2013 Prediction of Vddc noise level at PCB level <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | Figure D.2 \u2013 Good agreements on the noise envelope <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" EMC IC modelling – Models of integrated circuits for EMI behavioural simulation. Conducted emissions modelling (ICEM-CE)<\/b><\/p>\n |